Design Method for Digital Logic Circuits with Optimization for Dependability and Life Time

基于纳米技术的集成电路和系统显示出越来越高的脆弱性，一方面是短暂故障效应，另一方面是由于早期磨损导致的永久故障。容错计算技术已经存在了很长时间，但在大多数情况下，它们在设备和功耗方面代价高昂，或者仅适用于特定类型的故障。到目前为止，逻辑的内置自修复技术几乎没有实际应用。该项目的目标是根据个别电路、信号和子系统的具体需求，系统地将在线测试、容错甚至自我修复引入数字系统设计。这意味着设计技术迈出了新的一步，它必须尽可能地与工具和设计流程中的标准兼容。最后，该项目将首次实现在线测试、纠错和自我修复的优化组合，以可承受的成本延长使用寿命。

Integrated circuits and systems, based on nano-technologies, have shown a rising level of vulnerability with respect to transient fault effects on one side and permanent faults due to early wear-out on the other hand. Technologies of fault tolerant computing have been known for a long time, but they are in most cases costly in terms of devices and power consumption, or they are applicable only to specific types of faults. Technologies of built-in self repair for logic have found little practical application so far. The project targets a systematic introduction of on-line test, fault tolerance and even self repair into digital system design, depending on the specific demands for individual circuits, signals and sub-systems. This means a new step in design technology, which has to be as compatible as possible with standards in tools and design flows. Finally, the project will, for the first time, achieve an optimized combination of on-line-test and error correction and self repair for life-time extension at affordable cost.