SHF: Small: Automatic Generation of Cache Coherent Memory Systems for Multicore Processors

今天的计算机处理器被称为多核处理器，因为它们里面有多个处理器核心，所有这些核心都可以同时处理计算任务。这些核心使用称为高速缓存一致性的通信协议彼此共享数据，该协议确保这些核心使用的数据是最新的和正确的。高速缓存一致性协议是出了名的复杂和难以设计，而且它们至少在所有情况下都很难验证。由于其复杂性，当计算机行业创建新的处理器时，一致性协议占据了设计和验证资源的很大且不成比例的份额。此外，随着处理器核心在单个芯片上种类和数量的增加，设计一致性协议的难度也在增加。该项目正在开发一种新的工具，使计算机架构师能够快速、轻松地设计可证明是正确的高性能一致性协议。该工具有可能从根本上改变工业界和学术界设计协议的方式，从而使处理器设计更快、更便宜、更可靠。通过面向本科生的外展计划和研究奖学金计划，该项目将受益于女性、代表性不足的人群和本科生研究人员的贡献。随着处理器设计的变化--随着更多核心或不同类型的核心的增加，或者具有不同的预期通信模式--有动力创造新的一致性协议来适应这些变化。该项目正在开发一种新的工具ProtoGen+，用于自动化可验证的缓存一致性协议的设计。架构师只需提供简化的协议设计，即可省略层次结构和并发通信等复杂性。该工具采用这些简化的协议设计，并自动生成这些协议的高性能版本，从而对架构师隐藏了复杂性。然后，ProtoGen+输出复杂的并发协议。ProtoGen+大大减少了设计和验证工作，并最大限度地减少了设计错误的数量。ProtoGen+支持多种协议，包括具有层次化和异构性的协议。ProtoGen+还会生成避免协议死锁所必需的虚拟网络分配。这项工作的两个次要目标是探索与ProtoGen+兼容的协议空间，并产生与先前开发的可验证协议设计的Neo框架兼容的协议。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

Today’s computer processors are called multicore processors, because they have multiple processor cores in them, all of which can be working simultaneously on computational tasks. These cores share data with each other using a communication protocol called cache coherence, which ensures that the data used by these cores is up-to-date and correct. Cache coherence protocols are notoriously complicated and difficult to design, and they are at least as difficult to then verify as being correct in all situations. Because of their complexity, coherence protocols take a large and disproportionate share of the design and verification resources when the computer industry creates a new processor. Furthermore, the difficulty of designing coherence protocols is increasing as processor cores scale up in variety and number on a single chip. This project is developing a novel tool that enables computer architects to quickly and easily design high-performance coherence protocols that are provably correct. The tool has the potential to radically change the way that protocols are designed, in both industry and academia, and thus make processor design faster, cheaper, and more reliable. Through an outreach program and a research fellowship program for undergraduates, the project will benefit from the contributions of women, under-represented populations, and undergraduate researchers.As processor designs change--with the addition of more cores or different types of cores, or with different expected communication patterns--there are incentives to create new coherence protocols to suit these changes. Even if a new protocol is not a radical departure from previous protocols, designing it and validating it are arduous, bug-prone processes.This project is developing a novel tool, called ProtoGen+, for automating the design of verifiable cache coherence protocols. The architects need only provide simplified protocol designs that omit complexity like hierarchy and concurrent communications. The tool takes those simplified protocol designs and automatically generates the high-performance versions of those protocols, thus hiding the complexity from the architects. ProtoGen+ then outputs the complicated, concurrent protocol. ProtoGen+ greatly reduces design and verification effort and minimizes the number of design bugs. ProtoGen+ accommodates a wide range of protocols, including those with hierarchy and heterogeneity. ProtoGen+ also generates the virtual network assignments necessary to avoid protocol deadlock. Two secondary objectives of the work are to explore the space of protocols that are compatible with ProtoGen+ and to produce protocols that are compatible with the previously developed Neo framework for verifiable protocol design.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.