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SHF: Small: Using Coding Theory to Optimize the Representation of Information in Computer Architecture

SHF: Small: Using Coding Theory to Optimize the Representation of Information in Computer Architecture
SHF:小:利用编码理论优化计算机体系结构中的信息表示
批准号:
1421177
负责人:
Daniel Sorin
金额:
$45.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2014
资助国家:
美国
项目状态:
已结题
起止时间:
2014-08-01 至 2018-07-31

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中文摘要
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英文摘要
Computer systems process and store information, includinginstructions, inputs, and outputs. Computers represent, or "encode",this information with bits -- zeros and ones -- such that a givensequence of bits can describe a number, an instruction, a character toprint to the monitor, etc. The choice of bit patterns used to encodedifferent types of information impacts the performance, reliability,and energy-efficiency of a computer. This project -- which is aninterdisciplinary collaboration between a computer systems architectand an expert in information coding -- will develop new informationrepresentations that improve performance, reliability, andenergy-efficiency. This project will have both technical impact oncomputer system design and information coding, and it will impactsociety through its training of students (both graduate andundergraduate) and an outreach program that brings under-representedminorities to Duke for summer research experiences. This project will make technical advances in four main avenues.First, the project will develop new representations for theinformation that is stored in write-limited storage media like Flash,with the goal of extending its lifetime. A key coding technology inthis research thrust is coset coding, in which the system has multiplechoices for which codeword to write to the storage and can choose theoption that incurs the least wear. Second, the project will developnew codes, based on existing locally repairable codes, for writing toall types of storage that can suffer permanent failures. These codescan enable efficient, local repair of failures by minimizing thenumber of storage locations that must be accessed to perform therepair. Third, the project will develop new representations ofinstructions to improve performance and energy-efficiency. Inparticular, the project will develop new encodings of instructions forGPUs that enable useful work to be done even in the presence of branchdivergence. Fourth, the project will develop and apply network codingtechniques to improve the performance and reliability of communicationbetween processor cores.
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