SHF: Small: Shared Memory Architectures and Microarchitectures for Heterogeneous General-Purpose Chips

计算机行业目前正在生产和开发包含不同类型处理器核心的芯片。异构芯片的发展源于两个趋势：在每个芯片上压缩更多晶体管的能力，以及为特定目的使用特定核心的能效提高。本研究项目将同质芯片的核间通信系统和精确规格扩展到异构芯片。扩展同构通信范例的好处包括改进性能和提高能效，初步结果显示这两个指标都有数量级的改进。社会越来越多地依赖于计算机，从质量上提高它们的性能和能效对未来的计算平台至关重要。此外，通过扩展同质规范方法，该研究项目促进了异质芯片的芯片测试和验证，这是芯片开发行业努力的重要组成部分，并且简化了这些芯片的编程，这是当今计算中最大的挑战之一。这个研究项目包括两个技术重点。第一个推动力是异构芯片存储系统的发展。与其将异构芯片视为碰巧共享一个芯片的两个不同系统，不如将异构内核以一种系统的方式紧密集成，使内核之间的大多数通信能够通过片内缓存而不是片外内存执行。第二个研究重点是将计算机体系结构的概念——处理器行为的独立于实现的规范——从同构系统扩展到芯片范围的异构系统。本研究项目涉及异构处理器芯片的设计和实验评估，大部分实验工作采用全系统仿真和购买硬件上的实验。这个项目的贡献将是异构处理器芯片，具有显著更高的性能和功率效率，以及异构芯片的实现独立架构。社会将在个人电脑、智能手机和云提供的服务中使用异构处理器芯片。从质量上改进这些芯片将增强用户的计算体验，并使新的令人兴奋的计算应用成为可能。

The computing industry is currently producing and developing chips that include processor cores of different types. The move towards heterogeneous chips is due to two trends: the ability to squeeze more transistors on each chip and the improved power-efficiency of using specific cores for specific purposes. This research project extends the inter-core communication systems and precise specifications of homogeneous chips to heterogeneous chips. The benefits of extending homogeneous communication paradigms include improved performance and improved power-efficiency, and preliminary results show orders of magnitude improvements in both metrics. Society relies upon computers for ever more purposes, and qualitatively improving their performance and power-efficiency are critical to future computing platforms. Furthermore, by extending homogeneous specification methodologies, this research project facilitates chip testing and validation for heterogeneous chips, which is a significant fraction of industry effort in chip development, and eases the programming of these chips, which is among the biggest challenges in computing today. This research project consists of two technical thrusts. The first thrust is the development of memory systems for heterogeneous chips. Rather than treat a heterogeneous chip as two distinct systems that happen to share a chip, the goal is to closely integrate the heterogeneous cores in a systematic fashion that enables most communication between cores to be performed via on-chip caches rather than via off-chip memory. The second research thrust is to extend the notion of a computer architecture--an implementation-independent specification of a processor's behavior--from homogeneous systems to chip-wide heterogeneous systems. This research project involves the design and experimental evaluation of heterogeneous processor chips, and the bulk of the experimental work uses full-system simulation and experiments on purchased hardware. The contributions of this project will be heterogeneous processor chips that have significantly greater performance and power-efficiency, as well as implementation-independent architectures for heterogeneous chips. Society will be using heterogeneous processor chips in personal computers, in smartphones, and via cloud-provided services. Qualitatively improving these chips will enhance user computing experiences and enable new and exciting computing applications.