CAREER: SHF: Chiplet-Package Co-Optimizations for 2.5D Heterogeneous SoCs with Low-Overhead IOs

作为一种灵活、可扩展的超越摩尔的解决方案，2.5D芯片的设计正变得越来越流行，以提高集成电路芯片的计算性能。通过异构集成，每个IP块都可以使用最佳技术节点来实现，从而最大限度地提高设计灵活性和性能。然而，与单片2D芯片相比，缺点是芯片间通信带来了巨大的开销。与片上互连相比，封装线具有更大的寄生效应。因此，它们可能会降低2.5D系统的性能和能源效率。设计这些实体IOs既昂贵又耗时。如果没有通用的标准，异构组件就无法轻松集成，设计人员需要保守地保留较大的设计余量，这不可避免地导致非最佳设计和成本增加。传统的设计流程和CAD工具也无法捕获小芯片和封装之间的时序、功率和信号完整性属性。缺少低开销、低成本和可定制的IOs和设计工具大大减缓了这些先进封装技术的采用。该项目采用芯片-封装协同设计方法，将集成电路和封装设计结合起来，为异构开发提供无缝环境。目标是最大限度地减少芯片间性能开销，降低设计成本，探索2.5D系统的全部潜力，并展示最高的集成密度和能源效率。拟议的芯片设计工作和CAD工具将用于为学生提供教育材料，实践经验和客座讲座。该项目将通过一系列产业合作、大学预科教育、PI所在机构和阿肯色州的大学和研究生教育计划，为半导体研发领域急需的美国劳动力的发展做出贡献。项目产生的设计工具将是开源的，并与设计示例和文档一起打包。这种2.5D芯片-封装协同设计流程将消除芯片和封装之间的边界，并结合额外的设计合成、提取和优化步骤，以最大限度地降低开销和成本。IO合成将根据详细的提取结果创建并放置具有足够大小的小IO单元。主动封装合成将生成封装内缓冲器和重新定时器，以优化面积、长度和性能。芯片到封装耦合的整体和上下文提取将为同质和异构设计提供最高的精度。2.5D系统的制造和测试旨在确保与测量数据的真实验证。这种CAD流程将进一步打破低电压和高功率工程之间的界限，使Si逻辑和GaN/SiC功率转换的异构集成成为可能。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Design of 2.5D chiplets is becoming increasingly popular as a flexible and scalable More-than-Moore solution to push computational performance of integrated circuit chips. With heterogeneous integration, each IP block can be implemented using the optimum technology node, maximizing design flexibility and performance. However, a drawback compared with a monolithic 2D chip is the large overhead introduced by inter-chiplet communication. On-package wires have much larger parasitics compared with on-chip interconnects. Thus, they may reduce the performance and energy-efficiency of 2.5D systems. Designing these physical IOs are expensive and time-consuming. Heterogeneous components cannot be easily integrated without a commonly used standard, and designers need to conservatively reserve a large design margin, which inevitably results in non-optimum designs and increased costs. The timing, power, and signal integrity properties between chiplets and the package are also not captured by the traditional design flow and CAD tools. The missing low-overhead, low-cost, and customizable IOs and design tools significantly slow down the adoption of these advanced packaging techniques. This project uses a chiplet-package co-design methodology to combine IC and package designs and provide a seamless environment for heterogeneous development. The goal is to minimize inter-chiplet performance overhead, reduce design costs, explore the full potential of 2.5D systems, and demonstrate the highest integration density and energy efficiency. The proposed chip design efforts and CAD tools will be used to provide educational materials, hands-on experience, and guest lectures to students. The project will contribute to the development of much needed US workforce in the area of research and development of semiconductors via a diverse set of plans for industry collaboration, pre-college education, and college and graduate-level education at the PI's institution, and in the state of Arkansas. The design tools resulting from the project will be open-sourced and packaged with design examples and documentation. This 2.5D chiplet-package co-design flow will eliminate the boundary between chiplets and the package and combine additional design synthesis, extraction, and optimization steps to minimize overhead and costs. The IO synthesis will create and place small IO cells with just-enough sizing based on detailed extraction results. The active package synthesis will generate on-package buffers and re-timers to optimize area, wirelength, and performance. Holistic and In-Context extraction for chiplet-to-package coupling will provide the highest accuracy for both homogeneous and heterogeneous designs. The fabrication and testing of 2.5D systems is intended to ensure realistic validation with measured data. This CAD flow will further break the boundary between low-voltage and high-power engineering and enable computer-on-package with heterogeneous integration of Si logic and GaN/SiC power conversion.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.