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CRII: SHF: Error Resilient Asynchronous Architecture for Ultra-Low Power Energy Harvesting IoT Applications

CRII: SHF: Error Resilient Asynchronous Architecture for Ultra-Low Power Energy Harvesting IoT Applications
CRII:SHF:适用于超低功耗能量收集物联网应用的容错异步架构
批准号:
2153373
负责人:
Ashiq Sakib
金额:
$17.5万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2022
资助国家:
美国
项目状态:
未结题
起止时间:
2022-03-01 至 2025-02-28

项目摘要

项目成果

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中文摘要
翻译
该奖项全部或部分由《2021年美国救援计划法案》(公法117-2)资助。随着对自供电智能电子产品和无电池解决方案的需求增加,能量收集将成为未来的电源。能量收集装置利用来自环境资源或人类活动的能量。然而,由于不同能源的能量密度有限和能量分布不规律,这种自供电设备即使在波动的电源电压下也应该具有极高的能效和功能。如今,大多数基于传统同步(时钟)数字设计的设备都非常耗电,时钟占所消耗能量的很大一部分。此外,设备的小型化带来了重大的设计挑战,这使得时钟设计更容易受到电源电压变化的影响,不适合在收集能量的设备上运行。异步(无时钟)设计可以解决与时钟设计相关的功率效率低下的问题,并有可能通过能量收集将一整类应用程序带入可服务的领域。有了这个愿景,这个项目的主要目标是设计抗错误的异步电路,它可以创建一个场所来实现强大的、无监督的、免维护的、安全的、可持续的和低功耗的电子设备,用于不同领域的许多能量收集驱动的应用,如医疗、航天、国防、汽车、电力工业等。以及用于超低功耗应用的容错准延迟不敏感(QDI)异步架构,该架构可以执行节能计算并在无监督情况下提供对辐射引起的瞬态错误的保护。虽然存在许多用于同步设计的错误检测和缓解技术,但用于QDI异步电路的技术却很少。此外,现有的方法也有很大的局限性,比如无法确保完全的弹性,无法阻止QDI管道中的错误传播,无法规避导致延迟、能量和面积开销的重复,等等。本项目旨在通过两个阶段的研究来解决这些限制。第一阶段将侧重于1)系统地分析QDI异步电路的错误响应,2)开发一个可扩展和有效的正式框架,以识别数据路径和控制路径中的脆弱组件。第二阶段将利用第一阶段开发的框架,1)严格分析易受攻击的组件和关键路径,2)调查可能的架构修改,以实现完整的错误恢复能力,3)确保采取适当的行动,防止故障通过QDI管道传播,以及4)对新开发的架构进行成本/性能权衡分析。该奖项反映了美国国家科学基金会的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
This award is funded in whole or in part under the American Rescue Plan Act of 2021 (Public Law 117-2).As the demand for self-powered smart electronics and battery-less solutions increases, energy harvesting will be the power source of the future. Energy-harvesting devices operate on energy derived from ambient environmental sources or human activities. However, due to the limited energy density and irregular energy profile of different energy sources, such self-powered devices should be extremely energy-efficient and functional even under fluctuating supply voltages. Nowadays, most devices based on conventional synchronous (clocked) digital designs are extremely power-hungry, with the clock accounting for a significantly large portion of the consumed energy. Moreover, device miniaturization results in major design challenges, which makes clocked designs more susceptible to supply-voltage variations and unsuitable for devices operating on harvested energy. Asynchronous (clockless) designs can resolve the power inefficiencies associated with clocked designs, and have the potential to bring a whole class of applications into the domain serviceable by energy harvesting. With this vision, the primary objective of this project is to design error-resilient asynchronous circuits, which can create a venue to implement robust, unsupervised, maintenance-free, safe, sustainable, and low-power electronics for numerous energy harvesting-powered applications in different sectors, such as medical, space, defense, automobile, power industry, etc.The goal of this project is to develop a robust, reliable, and error-tolerant Quasi Delay Insensitive (QDI) asynchronous architecture for ultra-low power applications, which can perform energy-efficient computation and provide protection against radiation-induced transient errors in unsupervised scenarios. While numerous error-detection and -mitigation techniques exist for synchronous designs, there are very few for QDI asynchronous circuits. Also, the existing methods have major limitations, such as failure to ensure complete resilience, failure to halt error propagation in QDI pipelines, failure to circumvent duplication resulting in latency, energy, and area overhead, etc. This project aims to address these limitations by conducting research in two phases. The first phase will focus on 1) systematically analyzing the error response of QDI asynchronous circuits, and 2) developing a scalable and efficient formal framework to identify vulnerable components in both the data path and control path. The second phase will leverage the framework developed in the first phase to 1) critically analyze the vulnerable components and critical paths, 2) investigate possible architectural modifications for complete error-resilience, 3) ensure proper actions to prevent fault propagation through the QDI pipeline, and 4) perform cost/performance trade-off analysis of the newly developed architecture.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
期刊论文(3)
专著(0)
科研奖励(0)
会议论文
DOI: 10.3390/jlpea14010005
发表时间: 2024
期刊: Journal of Low Power Electronics and Applications
影响因子: 2.1
作者: [Mazumder, Dipayan, Datta, Mithun, Bodoh, Alexander C., Sakib, Ashiq A.]
通讯作者: Sakib, Ashiq A.
Error Resilient Sleep Convention Logic Asynchronous Circuit Design
容错睡眠约定逻辑异步电路设计
DOI: 10.1109/newcas57931.2023.10198041
发表时间: 2023
期刊: IEEE
影响因子: --
作者: [Datta, Mithun, Bodoh, Alexander, Sakib, Ashiq A.]
通讯作者: Sakib, Ashiq A.
Combining Relaxation With NCL_X for Enhanced Optimization of Asynchronous Null Convention Logic Circuits
将弛豫与 NCL_X 相结合以增强异步空约定逻辑电路的优化
DOI: 10.1109/access.2023.3318132
发表时间: 2023
期刊: IEEE Access
影响因子: 3.9
作者: [Khodosevych, Danylo, Bodoh, Alexander C., Sakib, Ashiq A., Smith, Scott C.]
通讯作者: Smith, Scott C.
国内基金
海外基金
天然超短抗菌肽Temporin-SHf衍生多肽的构效分析与抗菌机制研究
衔接蛋白SHF负向调控胶质母细胞瘤中EGFR/EGFRvIII再循环和稳定性的功能及机制研究
  • 批准号:
    82302939
  • 项目类别:
    青年科学基金项目
  • 资助金额:
    30万元
  • 批准年份:
    2023
  • 负责人:
    汪京京
  • 依托单位:
EGFR/GRβ/Shf调控环路在胶质瘤中的作用机制研究
  • 批准号:
    81572468
  • 项目类别:
    面上项目
  • 资助金额:
    60.0万元
  • 批准年份:
    2015
  • 负责人:
    邹健
  • 依托单位: