SHF: Small: Compiler and Architectural Techniques for Soft Error Resilience

由于技术规模，电子电路越来越容易受到辐射引起的软误差，也称为瞬态故障。软错误可能导致应用程序崩溃，甚至更糟糕的是，错误检测逻辑无法捕获的静默数据损坏（SDC），但可能导致应用程序产生不正确的输出。另一个严重的问题是检测到的不可恢复错误（DUE）的增加，这通常会直接影响任何计算机应用程序的可靠性。挑战在于以一种不会显著增加底层硬件的性能开销、功耗和复杂性的方式实现软错误弹性。为此，本项目设计和开发了低成本的软错误恢复硬件/软件协作技术。由此产生的人工制品和技术有望通过解决在存在软错误的情况下建立可靠计算系统的挑战，为国家的竞争力做出贡献。本研究涉及三个中间研究目标：设计新颖的微体系结构，基于基于传感器的软错误检测动态验证处理器核心执行的正确性，以低成本实现软错误恢复；设计一个编译器，在存在软错误时形成可验证和可恢复的区域，并提供相关的程序分析技术；并设计和开发编译器优化和微架构技术，以显著减少验证开销。该项目将为实现软错误弹性计算系统创造工具和技术，为容错研究界做出根本性贡献。采用由此产生的编译器和微体系结构技术将影响到需要正确计算结果的任何学科，从而需要可靠的计算系统，涵盖从移动设备到高性能大规模计算系统。因此，使用由此产生的技术将使当前和新兴应用程序的执行更加可靠，从而直接影响我们的生活方式。

Due to technology scaling, electronic circuits are becoming more susceptible to radiation-induced soft errors also known as transient faults. Soft errors may lead to application crash or even worse, silent data corruptions (SDC) that are not caught by the error detection logic but may cause the application to produce incorrect output. Another serious problem is the rise of detected unrecoverable errors (DUE) that often directly impact the reliability of any computer applications. The challenge is to achieve soft error resilience in a way that does not significantly increase the performance overhead, power consumption, and complexity of underlying hardware. To this end, this project designs and develops low-cost hardware/software cooperative techniques for soft error resilience. The resulting artifacts and technologies are expected to contribute to the nation's competitiveness by addressing the challenge of building reliable computing systems in the presence of soft errors.This research involves three intermediate research goals: design novel microarchitecture, that dynamically verifies the correctness of the processor core execution based on sensor-based soft error detection, to achieve soft error resilience at low cost; design a compiler that forms verifiable and recoverable regions in the presence of soft errors and provides relevant program analysis techniques; and design and develop compiler optimization and microarchitectural techniques that significantly reduce the verification overhead. This project will create tools and technologies for realization of soft error resilient computing systems, contributing fundamentally to the fault tolerance research community. Adoption of the resulting compiler and microarchitectural techniques will impact a broad range of any disciplines that need correct computation results thus requiring reliable computing systems, covering from mobile devices to high-performance large-scale computing systems. Consequently, use of the resulting technologies will make the execution of current and emerging applications much more reliable, and therefore directly affect our way of life.