Exploring the Limits of Scaling and 3D-integration for Edge-contacted Nanomaterial-based Transistors

非技术性：这个NSF项目旨在解决与半导体纳米材料和导电金属之间的电界面有关的长期问题。纳米材料显示出很大的希望，使摩尔定律的延续，这涉及到使用集成电路的计算能力的增加。通过将纳米材料用于晶体管中的半导体，这些核心计算设备可以扩展到更小的尺寸，与传统半导体（如硅）相比，性能更高。然而，关于如何控制纳米材料和接触金属之间的电流流动仍然存在许多问题。该项目将通过使用定制设计的器件结构来研究各种金属-纳米材料界面的电流行为和控制，从而为该领域带来变革。使用所谓的边缘接触几何形状，将研究n型和p型纳米材料晶体管，并最终在3D集成电路中进行演示。该项目的智力价值包括解决与如何在缩放尺寸的金属-纳米材料界面控制电流有关的科学问题。从这些研究中产生的新见解将通过增加对缩放限制的理解和实现设备3D集成的新方法的证据来推进纳米电子学领域。该项目更广泛的影响包括未来集成电路设备的进步以及工程专业学生的参与。该项目的进步可以使晶体管的新集成电路设计能够降低数据中心等高能耗应用的功耗。通过这个项目，两名来自工程学代表性不足的群体的研究生将得到支持，沿着几项新的外联举措，使K-12和本科生参与研究工作。 技术：纳米材料为未来的晶体管技术提供了许多优势。然而，在纳米材料晶体管的制造和集成方面仍然存在科学未知数和障碍。该项目旨在解决与2D过渡金属二硫属化物（TMD）和1D碳纳米管（CNT）的金属-纳米材料接触界面相关的几个长期存在的问题。将追求四个不同的目标，每个目标都与金属-纳米材料接触的一个特定方面有关。第一个目标是解决2D晶体管中的接触门控是否影响接触长度缩放行为的问题。迄今为止，几乎所有的器件都包括底栅结构，其中栅极与源极/漏极接触重叠。这会对金属触点下方的半导体产生门控效应，这种效应的影响已经被假设，但从未进行过实验研究-这种研究将使用大量二硫化钼（MoS 2）器件进行，这些器件设计用于具有和不具有重叠栅极的特性。第二个目标是确定在制造1D边缘接触到2D TMD期间环境空气暴露的影响。边缘接触是最可扩展的，因为它们仅在金属的边缘处突然与纳米材料接触;然而，关于这些接触结构的报道很少，并且这些报道包含关于金属接触沉积之前空气暴露的影响的相互矛盾的声明。将使用2D MoS 2和二硒化钨（WSe 2）对四种不同的边缘接触形成工艺进行系统和参数研究。第三个目标将是开发第一个用于CNT的低温（400 ℃）边缘接触形成工艺，该工艺提供与n型MoS 2器件耦合良好的p型器件。最后，第四个目标是将边缘接触的n型MoS 2晶体管与边缘接触的p型CNT晶体管集成，以证明垂直单片集成是后端线（BEOL）兼容的;更重要的是，这种证明的方法还通过在接触通孔的同一步骤中形成边缘接触来从工艺中去除一个掩模层。总的来说，追求这些目标的结果将是对适用于广泛设备应用的金属纳米材料接触的关键科学见解。该奖项反映了NSF的法定使命，并被认为值得通过使用基金会的知识价值和更广泛的影响审查标准进行评估来支持。

Nontechnical:This NSF project aims to address longstanding questions related to the electrical interface between semiconducting nanomaterials and conducting metals. Nanomaterials show great promise for enabling a continuation of Moore’s law, which relates to the increase in computational capability using integrated circuits. By using nanomaterials for the semiconductor in transistors, these core computing devices can be scaled to smaller dimensions with increased performance compared to traditional semiconductors, such as silicon. Yet, there remain many questions about how electrical current flow is controlled between nanomaterials and contact metals. This project will bring transformative change to the field by using custom-designed device structures to study the behavior and control of electrical current at various metal-nanomaterial interfaces. Using what is known as an edge-contact geometry, both n-type and p-type nanomaterial-based transistors will be studied and ultimately demonstrated in a 3D integrated circuit. The intellectual merits of the project include addressing scientific questions related to how current is controlled at metal-nanomaterial interfaces at scaled dimensions. The new insights generated from these studies will advance the field of nanoelectronics through increased understanding of the scaling limits and evidence for a new approach to achieving 3D integration of devices. The broader impacts of the project include the advancement of devices for future integrated circuits and the engagement of students underrepresented in engineering. The advancements in this project can enable new integrated circuit designs for transistors to lower power consumption in energy-hungry applications such as data centers. Through this project, two graduate students from groups underrepresented in engineering will be supported, along with several new outreach initiatives to involve K-12 and undergraduates in the research effort. Technical:Nanomaterials offer many advantages for use in future transistor technologies. Yet, there remain scientific unknowns and obstacles to the fabrication and integration of nanomaterial-based transistors. This project seeks to address several longstanding questions related to metal-nanomaterial contact interfaces for 2D transition metal dichalcogenides (TMDs) and 1D carbon nanotubes (CNTs). Four distinct goals will be pursued, each relating to a specific aspect of metal-nanomaterial contacts. The first goal will be to address the question of whether contact gating in 2D transistors influences the contact length scaling behavior. Virtually all devices to date have included bottom-gate structures with the gate overlapping the source/drain contacts. This produces a gating effect on the semiconductor beneath the metal contacts and the influence of this effect has been hypothesized but never experimentally studied – such a study will be pursued with a large set of Molybdenum disulfide (MoS2) devices designed for characterization with and without an overlapping gate. The second goal will be to determine the impact of ambient air exposure during the fabrication of 1D edge contacts to 2D TMDs. Edge contacts are the most scalable because they only interface with the nanomaterial abruptly at the edge of the metal; however, there are very few reports of these contact structures and these contain conflicting claims regarding the influence of air exposure prior to metal contact deposition. A systematic and parametric study will be performed on four distinct edge-contact formation processes using 2D MoS2 and Tungsten diselenide (WSe2). The third goal will be to develop the first low-temperature (400 C) edge-contact formation process for CNTs, which offer p-type devices that couple well with n-type MoS2 devices. Finally, the fourth goal will be to integrate the edge-contacted n-type MoS2 transistors with the edge-contacted p-type CNT transistors to demonstrate vertical monolithic integration that is back-end-of-line (BEOL) compatible; what’s more this demonstrated approach also cuts one masking layer out of the process by having the edge contacts formed in the same step as the contact vias. Overall, the results of pursuing these goals will be key scientific insights into metal-nanomaterial contacts applicable to a broad range of device applications.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.