CAREER: Algorithm-Hardware Co-design of Efficient Large Graph Machine Learning for Electronic Design Automation

在电子设计自动化（EDA）流程中更早地估计功率、性能和面积（PPA）将提高芯片设计的结果质量（QoR）和可靠性。经典的分析或启发式方法可能很难进行微调，特别是对于复杂的问题。机器学习（ML）方法已被证明是解决这些问题的有效方法。图神经网络（gnn）之所以受到欢迎，是因为它们是表示EDA流中基本对象的最自然的方法之一。然而，随着设计复杂性和芯片容量的增加，EDA中超大图形与通用硬件（如主流图形处理单元（gpu））的支持不足之间的性能差距越来越大。该项目旨在通过全面开发高效和可扩展的计算范式，加快各种EDA任务上的大型图机器学习。这个项目的新颖之处在于EDA领域知识感知图机器学习、训练加速以及算法-硬件协同设计和优化。该项目更广泛的意义和重要性包括：(1)推进芯片设计中的机器学习领域，这在国家人工智能计划中得到了强调；(2)加深对EDA领域知识、图学习和GPU加速之间相互作用的理解；(3)通过相关项目丰富计算机工程课程，促进本科生、弱势群体和K-12学生参与STEM领域。该项目将为高效、可扩展和实用的算法-硬件协同优化解决方案开发一个设计范例，以使用单个GPU显著加速EDA任务上的大型图形机器学习。该项目包括三个连贯的研究重点：(1)开发一种算法-硬件协同优化范式，重点是重新研究EDA图特征，引入分区和选择性再生长方法，以及定制GPU内核，以便使用单个GPU在EDA任务上进行统一的图机器学习；(2)采用平铺可逆结构进行低内存训练，提高单GPU大电路图神经网络（GNN）训练速度，设计maxK非线性函数降低计算成本；(3)结合EDA领域知识、图学习和硬件优化，协同搜索合适的硬件原语和GNN压缩策略，紧密利用电路图的独特属性。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Estimating Power, Performance, and Area (PPA) earlier in the electronic design automation (EDA) flow would improve the Quality of Results (QoR) and reliability in chip design. The classical analytical or heuristic methods can be challenging to fine-tune, especially for complex problems. Machine learning (ML) methods have proven to be effective in addressing these problems. Graph Neural Networks (GNNs) have gained popularity since they are among the most natural ways to represent the fundamental objects in the EDA flow. However, with increased design complexity and chip capacity, an increasing performance gap exists between the extremely large graphs in EDA and the insufficient support from general-purpose hardware, such as mainstream graphics processing units (GPUs). This project aims to expedite the large graph machine learning on various EDA tasks, through a full-fledged development of efficient and scalable computing paradigms. This project's novelties are EDA domain knowledge-aware graph machine learning, training acceleration, and algorithm-hardware co-design and optimization. The project's broader significance and importance include: (1) to advance the field of machine learning in chip design, highlighted in National Artificial Intelligence Initiative; (2) to deepen the understanding of interactions among EDA domain knowledge, graph learning, and GPU acceleration; (3) to enrich the computer engineering curriculum and promote participation from undergraduates, underrepresented groups, and K-12 students in STEM fields through relevant programs.The project will develop a design paradigm for efficient, scalable and practical algorithm-hardware co-optimized solutions to significantly accelerate large graph machine learning on EDA tasks using a single GPU. This project consists of three coherent research thrusts: (1) to develop an algorithm-hardware co-optimized paradigm, focusing on restudying EDA graph features, introducing partitioning and selective re-growth methods, and tailoring GPU kernels for unified graph machine learning on EDA tasks using a single GPU; (2) to speed up single GPU for large circuit Graph Neural Network (GNN) training by implementing a tiled reversible architecture for low-memory training, and designing a maxK nonlinearity function to reduce computation costs; (3) to jointly integrate EDA domain knowledge, graph learning, and hardware optimizations to co-search for the appropriate hardware primitives and GNN compression strategies, as well as closely leverage the unique properties of circuit graphs.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.