Time-Variant Architectures and Stabilty Criteria for Incremental Sigma-Delta ADC(TASC for IADC )

拟议的研究项目的目的是对增量Σ-Δ A/D转换器的系统化设计过程。这种类型的A/D转换器在现有技术中显示出特别的潜力，特别是具有小到中等的转换速率和非常高的分辨率;最近的工作表明，全新的快速ADC可以根据增量ADC的原理工作。然而，以前的设计方法限于经验设计规则，主要应用连续工作的知识，正常的Σ-Δ转换器，没有包括非理想的选项，因此不提供系统的设计过程的可能性。例如，在初步工作中，由于增量工作方法，这种类型的ADC有可能使用具有时间依赖非理想性的时变架构。实施周期开始时的低非理想性和实施周期结束时的高非理想性允许以几乎相同的性能水平保存性能。然而，这种时变架构的设计过程及其与时变非理想性相比的优化尚未得到充分研究。此外，增量Σ-Δ调制器（用连续时间环路滤波器实现）是时变的混合离散-连续时间系统，其由于内部量化而高度非线性。尽管已经描述了用于自由运行Σ-Δ调制器的稳定性行为的许多分析方法，但是在实践中通常仅使用最简单的变体，其在仿真中通常被示出为不适合于增量ADC。因此，本研究项目将不仅关注增量转换器时变架构的优化设计过程以及其中包含的时变非理想性，而且关注其稳定性行为。稳定性指标适用于增量模式的操作和比较通常的自组织指标的自由运行的调制器。其目的是显着改善设计过程，并最终提高功率效率的增量Σ-Δ转换器的电路设计。

The proposed research project aims towards a systematic design process for incremental sigma-delta A/D converters. This type of A/D converter shows particular potential in the prior art, especially with small to moderate conversion rates and very high resolutions; Recent work shows that completely new, fast ADCs can work on the principle of incremental ADCs. However, previous design approaches are limited to empirical design rules, mostly apply the knowledge of continuously working, normal sigma-delta converters, do not have the option of including non-idealities, and therefore do not offer the possibility of a systematic design process. In preliminary work it was e.g. shown that this type of ADC has the potential to use time-variant architectures with time-dependent non-idealities due to the incremental working method. Low non-idealities at the beginning and high non-idealities at the end of an implementation cycle allow performance to be saved with almost the same level of performance. However, the design process for such time-variant architectures and their optimization compared to time-variant non- idealities has not yet been fully researched. In addition, the incremental sigma-delta modulator (implemented with a continuous- time loop filter) is a time- varying, mixed discrete-continuous-time system that is highly non- linear due to the internal quantization. Although many analysis methods for the stability behavior of free- running sigma-delta modulators have been described, only the simplest variant is often used in practice, which has often been shown in simulations to be unsuitable for incremental ADC. For this reason, this research project will focus not only on the optimal design process for time-variant architectures of incremental converters and the inclusion of time- variant non-idealities therein, but also on their stability behavior. Stability metrics are applied for the incremental mode of operation and compared to the usual ad-hoc metrics of free running modulators. The intention is to significantly improve the design process and ultimately the power efficiency for the circuit design of incremental Sigma Delta converters.