Design of Hardware Transactional Memory for Usage in Embedded Systems

事务性内存应用乐观同步来提高并行性，从而提高多核处理器上的执行性能。此外，事务性内存通过避免死锁简化了并行应用程序的可编程性。虽然硬件事务性内存在当前的桌面和服务器处理器中可用，例如Intel Haswell或IBM BlueGene/Q-和Power8处理器，但嵌入式处理器的实现并不存在，尽管它有进一步的好处：避免优先级反转和支持容错执行。这个项目的目标是研究事务内存在嵌入式系统中的部署。我们将设计一个硬件事务性内存，并将其集成到当前的嵌入式多核处理器中。应系统地研究以下方面：(1)支持并行任务的实时事务乐观同步；(2)嵌入式系统的事务管理控制；(3)利用事务性内存的检查点能力进行容错执行。

Transactional Memory applies optimistic synchronization to increase parallelism and therefore execution performance on multi-core processors. Moreover, Transactional Memory simplifies programmability of parallel applications by its deadlock avoidance. While Hardware Transactional Memory is available in current desktop and server processors as e.g. Intel Haswell or IBM BlueGene/Q- and Power8 processors, implementations for embedded processors do not exist despite further beneficial properties: avoidance of priority inversion and support of fault-tolerant execution.Target of this project is to investigate the deployment of Transactional Memory in embedded systems. We will design a Hardware Transactional Memory and integrate it into a current embedded multi-core processor. The following aspects shall be systematically investigated: (1) support of real-time capable transactions optimistic synchronization of parallel tasks, (2) transaction management control for embedded systems, and (3) fault-tolerant execution by exploiting the checkpointing ability of Transactional Memory.