Improving the Long-Term Reliability of Digital Organic Circuits (ILDOC)

提出的研究项目的主要目标是通过延长预期电路寿命来提高有机电路在实际应用中的适用性。我们打算通过两个主要策略来解决电路老化的紧迫问题，这两个策略需要在技术问题和电路设计方面进行创新：第一，通过改进有机n沟道器件来增加可行拓扑的数量，同时并行优化数字门拓扑。在电路设计方面，这将需要首次报道关于老化感知可靠性的可能的门拓扑结构的系统表征、评估和优化。作为关键结果，我们的目标是找到并实现对器件老化引起的参数漂移的敏感度最低的门设计的最有前途的候选者。我们评估了关键器件在栅极偏置应力下的暴露程度，这是器件老化的最关键参数。在目前的有机技术中，栅极设计的一个主要障碍是p沟道和n沟道晶体管性能之间的强烈不对称。因此，为了扩大电路设计的设计空间，我们的目标是在迁移率和偏置应力稳定性方面提高n沟道晶体管的性能，使其更接近p沟道器件。为了实现这一目标，引入新的半导体材料和优化制造工艺将是必要的。作为提高电路寿命的一种并行方法和第二种策略，我们将首次探索有机电路低电压设计的前景。由于器件老化表现出与栅偏压水平的指数关系，降低电源电压一方面是一种非常有希望的提高寿命的方法。另一方面，工艺可变性(匹配)阻碍了在低电压下的操作。这将再次需要仔细评估栅极拓扑，以找到最有希望的低电压操作候选者。此外，还需要研究可靠性方面的最佳电源电压、必要的性能权衡以及可实现的电路寿命改进。同时，晶体管器件工程将专门针对低电源电压下的运行进行优化。这将需要更好地了解使用不同的栅电介质和相应的不同材料属性带来的权衡，特别是关于迁移率、阈值电压和偏置应力稳定性等参数。这一系列器件将用于电路级分析，这一方面将大大拓宽电路设计的设计空间；另一方面，它还将允许从电路角度对提供最佳性能折衷的晶体管实现进行评估。

The main objective of the proposed research project is to improve the applicability of organic circuits in real-life applications by increasing the expected circuit lifetime. We intend to tackle the pressing issue of circuit aging with two main strategies, which require innovations both on technological issues as well as on circuit design aspects: First, by increasing the number of feasible topologies by means of improving the organic n-channel devices whilst in parallel optimizing the digital gate topologies. On the side of the circuit design, this will require the first reported systematic characterization, evaluation and optimization of possible gate topologies with regard to aging-aware reliability. As key result, we aim to find and implement the most promising candidates for gate design with the lowest susceptibility to the parameter shifts induced by device aging. We evaluate the exposure of the critical devices to gate bias stress, which is the most critical parameter for device aging. A major impediment for the design of gates in current organic technologies is the strong asymmetry between p- and n-channel transistor performance. To widen the design space available for circuit design, we therefore aim to improve the n-channel transistor performance in terms of mobility and bias stress stability to bring it closer to the one of the p-channel device. Incorporation of new semiconductor materials and optimization of the fabrication process will be necessary to achieve this goal.As a parallel approach and second strategy for circuit lifetime enhancement, we will for the first time explore the prospects of low-voltage design in organic circuits. As device aging exhibits an exponential dependence on the gate bias levels, the reduction of supply voltage is on the one hand an extremely promising approach for lifetime improvement. On the other hand, process variability (matching) hinders operation at low voltages. This will again require careful evaluation of gate topologies to find the most promising candidates for low-voltage operation. Furthermore, the optimum supply voltage with respect to reliability, the necessary performance trade-offs and the achievable improvements in circuit lifetime will need to be investigated. In parallel, the transistor device engineering will be optimized specifically for operation at low supply voltages. This will require a better understanding of the trade-offs that come with the use of different gate dielectrics and the corresponding differing material properties, especially regarding parameters like mobility, threshold voltage and bias stress stability. This range of devices will be used in the circuit-level analysis, which on one hand will considerably broaden the design space for circuit design; on the other hand, it will also allow an evaluation of transistor implementations which offer the best performance trade-off from a circuit point of view.