Realization of a high speed hardware compile engine for multiple languages

为了使程序高速运行，编译是一个非常重要的过程，它将源程序转换为经过优化的机器代码。然而，编译占用程序开发系统中的计算机的非常大量的处理时间。这一趋势在研究和教育用途中更高。这种情况意味着我们可以通过减少编译时间，将其作为一个独立的硬件单元从主机处理器中分离出来来提高系统性能。我们的研究目标是实现一个硬件编译引擎，它可以非常快地编译源程序，例如几十倍的速度。目前的编译器实现技术在软件基础上似乎已经足够成熟。因此，我们分析了这些技术是否与硬件实现相匹配。在硬件数据库上，详细的并行处理很容易被合并以提高速度。高速查表可以加快处理速度。部分技术是从上一个项目的直接执行计算机上引进的。硬件编译器的设计原则是（1）语言灵活性，（2）高速执行，（3）模块化设计。实际上，整个硬件分为四个功能单元：词法单元、语法分析单元、语义单元和代码生成器。这些装置采用管道连接，并联运行。词法单元的基本设计继承了直接执行计算机的设计，但简化了，速度也有点慢。分析器是在LR（1）基础上设计的，它基本上接受YACC分析表。对于语义分析器来说，并行分析是为了解决流水线的瓶颈问题。

In order to execute a program at high speed, compilation is a very important process which transforms the source program into machine codes with optimization. However, the compilation takes a very large amount of the processing time of the computer in the program development system. This tendency is higher for the reseach and educational uses. This situation implies that we can increase the system performance by reducing compiling time, seperating it as a independent hardware unit from the host processor. Our reseach objective is to realize a hardware compile engine which can compile a source program very fast, e.g several ten times faster. Current complier implementation technology seems to be enough matured on software basis. Therefore, we analyzed these technology whether they are matched with hardware realization. On haredware dasis, detailed parallel processing is easily incorporated for speed-up. High speed table search can accelerate the processing speed. Some technolygy has been imported from the direct-execution computer of our preceding project. The design principles of the hardware complier is (1) language flexibility, (2) high-speed execution, and (3) modular design. Actually, the entire hardware is devided into four functional units: lexical unit, parsing unit, semantic unit, and code generator. These units are connnected in pipeline, and operated in parallel. The basic design of the lexical unit is inherited from that of the diret-execution computer, but simpified and a little bit slowed. The parser is designed on LR(1) basis which basically accepts the YACC parsing table. For the sematic analyzer, parallel analysis is to solve the buttle neck of the pipeline.