Researches on the Design of Highly Reliable High-Speed Arithmetic Circuits with Redundant Coding

研究了高可靠的高速冗余编码算法电路的设计。(1)对带有冗余编码的算术运算的硬件算法及基于这些算法的故障相关电路设计；(2)电路的设计验证和测试生成，得到了以下研究成果：基于先前提出的冗余二进制表示和剩余码的除法算法，设计了一种在线错误检测快速阵列除法器。提出了一种冗余表示模乘法的快速硬件算法。具有大模数的模乘法在公钥密码系统中得到了广泛的应用。我们阐明了冗余二进制表示的冗余性的各种性质。提出了一种时间符号仿真方法作为逻辑电路时序验证的新方法。并在此基础上实现了仿真系统和结果分析系统。针对正则时间逻辑的可满足性问题，我们设计了一种算法，并对之前提出的算法进行了形式化验证。提出了一种基于矢量处理器的动态二维并行快速故障仿真方法，并在此基础上实现了故障模拟器。我们还提出了一种使用随机模式生成测试模式的方法，并在此基础上实现了一个程序。给出了一种利用线性逻辑电路对组合电路进行局部穷举测试的有效方法。研究了逻辑函数的素蕴涵的生成方法、逻辑函数的表示方法和硬件设计语言，取得了一定的成果。

We conducted researches for the design of highly reliable high-speed arithmetic circuits with redundant coding.For (1) hardware algorithms for arithmetic operations with redundant coding and fault torelant design of circuits based on them and.(2) design verification of circuits and test generation, we got the following research results:1. We designed an on-line error-detectable fast array divider based on a division algorithm with a redundant binary representation and a residue code which we had previously proposed.2. We proposed a fast hardware algorithm for modular multiplication with a redundant representation. Modular multiplication with a large modulus is widely used in public key cryptosystems.3. We clarified various properties of the redundancy of a redundant binary representation.4. We proposed a time-symbolic simulation method as a new method for timing verification of logic circuits. We also implemented a simulator based on the method and a result analysis system.5. We designed an algorithm for satisfiability problems of regular temporal logic, which we had proposed before for formal verification.6. We presented a dynamic two-dimensional parallel method for fast fault simulation using a vector processor and implemented a fault simulator based on the method. We also presented a test pattern generation method using random patterns and implemented a program based on the method.7. We showed an efficient method for locally exhaustive testing of combinational circuits using linear logic circuits.We also researched on a method for generating prime implicants of logic functions, a representation method for logic functions and a hardware design language and got some results.