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Basic Research on High-Speed Boolean Function Manipulator

Basic Research on High-Speed Boolean Function Manipulator
高速布尔函数操纵器的基础研究
批准号:
05452352
负责人:
YAJIMA Shuzo
金额:
$4.35万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for General Scientific Research (B)
财政年份:
1993
资助国家:
日本
项目状态:
已结题
起止时间:
1993 至 1994

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中文摘要
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英文摘要
We have carried out basic research on high-speed manipulation of Boolean functions based on binary decision diagrams.1.Algorithms and Complexity of Manipulating Binary Decision DiagramsWe have propsed highly parallel algorithms for reduction and Booleam operations, which are basic Boolean function manipulation based on binary decision diagrams (BDDs), and clarified their computational complexity. On the expressive power of BDDs, we have defined the class of Boolean functions expressible by polynomial size BDDs and compared it with the classes based on Turing machines. We have also studied on the size of BDDs representing threshold functions.2.High-Speed Boolean Function ManipulatorWe have propsed and experimented a method using secondary memory to manipulate very large shared BDDs (SBDDs) which cannot be stored in the main memory. Breadth-first manipulation of SBDDs is adopted in this method. We have also developed a parallel method to manipulate SBDDs on content sddressable memories (CAMs). It seems that very high parallelism can be realized using CAMs.3.Computer Aided Logic Design Based on Boolean ProcessingWe have applied Boolean function manipulation based on SBDDs to computer aided logic design, First, we proposed a method to generate compace test sequences for scan-based seaquential circuits. The second one is the application to the several state assignment methods for asynchronous sequential circuits. As an application for the problems not in the field of logic design, we have proposed some methods to solve combinatorial problems using Boolean processing.
期刊论文(44)
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会议论文
Shuzu YAJIA: "Minimum One-Shot State Assignment for Asynchronous Sequential Machines Using BDD" Trans.Information Processing Society Japan. Vol.35, No.9. 1888-1899 (1994)
Shuzu YAJIA:“使用 BDD 的异步顺序机的最小单次状态分配”Trans.Information Process Society Japan。
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KWON,Yong-Jin: "Minimum Single Transition-Time-Assignments for Asynchronous Sequential Circuits Using BDD" 情報処理学会論文誌. 35-2. 352-357 (1994)
KWON, Yong-Jin:“使用 BDD 的异步时序电路的最小单次转换时间分配”,日本信息处理学会汇刊 35-2 (1994)。
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Kiyoharu HAMAGUCHI: "Tne Complexity of Optimal Variable Ordering Problems of Shared Binary Decision Diagrams" Proceedings of 4th International Symposium on Algorithms and Computation(ISAAC'93). 389-398 (1993)
Kiyoharu HAMAGUCHI:“共享二元决策图的最优变量排序问题的复杂性”第四届国际算法与计算研讨会 (ISAAC93) 论文集。
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Kiyoharu HAMAGUCHI: "Another Look at LTL Model Checking" Proceedings of Conference on Computer-Aided Verification. 415-427 (1993)
Kiyoharu HAMAGUCHI:“LTL 模型检查的另一种看法”计算机辅助验证会议论文集。
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29
    Research on Development of Formal Logic Design Verifier for Microprocessors
    • 批准号:
      07558155
    • 项目类别:
      Grant-in-Aid for Scientific Research (A)
    • 资助金额:
      $1.41万
    • 财政年份:
      1995
    • 负责人:
      YAJIMA Shuzo
    • 依托单位:
    Research on Formal Verifier of Logic Design Based on Temporal Logic
    • 批准号:
      05558030
    • 项目类别:
      Grant-in-Aid for Developmental Scientific Research (B)
    • 资助金额:
      $6.85万
    • 财政年份:
      1993
    • 负责人:
      YAJIMA Shuzo
    • 依托单位:
    Research on Development of Logic Synthesizer and Design Verifier for Sequential Circuits Based on Boolean Function Manipulation
    • 批准号:
      03555074
    • 项目类别:
      Grant-in-Aid for Developmental Scientific Research (B)
    • 资助金额:
      $5.31万
    • 财政年份:
      1991
    • 负责人:
      YAJIMA Shuzo
    • 依托单位:
    Research on Efficient Manipulation of Boolean Functions Using Shared Binary Decision Diagrams and Its Application to Computer Aided Logic Design
    • 批准号:
      02452162
    • 项目类别:
      Grant-in-Aid for General Scientific Research (B)
    • 资助金额:
      $3.71万
    • 财政年份:
      1990
    • 负责人:
      YAJIMA Shuzo
    • 依托单位:
    海外基金