Basic Research on High-Speed Boolean Function Manipulator
高速布尔函数操纵器的基础研究
基本信息
- 批准号:05452352
- 负责人:
- 金额:$ 4.35万
- 依托单位:
- 依托单位国家:日本
- 项目类别:Grant-in-Aid for General Scientific Research (B)
- 财政年份:1993
- 资助国家:日本
- 起止时间:1993 至 1994
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
We have carried out basic research on high-speed manipulation of Boolean functions based on binary decision diagrams.1.Algorithms and Complexity of Manipulating Binary Decision DiagramsWe have propsed highly parallel algorithms for reduction and Booleam operations, which are basic Boolean function manipulation based on binary decision diagrams (BDDs), and clarified their computational complexity. On the expressive power of BDDs, we have defined the class of Boolean functions expressible by polynomial size BDDs and compared it with the classes based on Turing machines. We have also studied on the size of BDDs representing threshold functions.2.High-Speed Boolean Function ManipulatorWe have propsed and experimented a method using secondary memory to manipulate very large shared BDDs (SBDDs) which cannot be stored in the main memory. Breadth-first manipulation of SBDDs is adopted in this method. We have also developed a parallel method to manipulate SBDDs on content sddressable memories (CAMs). It seems that very high parallelism can be realized using CAMs.3.Computer Aided Logic Design Based on Boolean ProcessingWe have applied Boolean function manipulation based on SBDDs to computer aided logic design, First, we proposed a method to generate compace test sequences for scan-based seaquential circuits. The second one is the application to the several state assignment methods for asynchronous sequential circuits. As an application for the problems not in the field of logic design, we have proposed some methods to solve combinatorial problems using Boolean processing.
我们对基于二元决策图的布尔函数的高速运算进行了基础研究。1.二元决策图运算的算法和复杂性我们提出了基于二元决策图的基本布尔函数运算--约简和布尔运算的高度并行化算法,并阐明了它们的计算复杂性。在BDDS的表示能力方面,我们定义了可用多项式大小BDDS表示的布尔函数类,并将其与基于图灵机的类进行了比较。2.高速布尔函数管理器我们提出并实验了一种使用辅助内存来处理无法存储在主内存中的超大共享BDd(SBDd)的方法。该方法采用广度优先的方法处理SBDDS。我们还开发了一种并行方法来操作内容可寻址存储器(CAM)上的SBDD。基于布尔处理的计算机辅助逻辑设计我们将基于SBDDS的布尔函数运算应用到计算机辅助逻辑设计中,首先,我们提出了一种生成基于扫描的海洋电路的紧凑测试序列的方法。二是对异步时序电路的几种状态分配方法的应用。作为对非逻辑设计领域问题的应用,我们提出了一些利用布尔处理来解决组合问题的方法。
项目成果
期刊论文数量(44)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
Shuzu YAJIA: "Minimum One-Shot State Assignment for Asynchronous Sequential Machines Using BDD" Trans.Information Processing Society Japan. Vol.35, No.9. 1888-1899 (1994)
Shuzu YAJIA:“使用 BDD 的异步顺序机的最小单次状态分配”Trans.Information Process Society Japan。
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KWON,Yong-Jin: "Minimum Single Transition-Time-Assignments for Asynchronous Sequential Circuits Using BDD" 情報処理学会論文誌. 35-2. 352-357 (1994)
KWON, Yong-Jin:“使用 BDD 的异步时序电路的最小单次转换时间分配”,日本信息处理学会汇刊 35-2 (1994)。
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Kiyoharu HAMAGUCHI: "Tne Complexity of Optimal Variable Ordering Problems of Shared Binary Decision Diagrams" Proceedings of 4th International Symposium on Algorithms and Computation(ISAAC'93). 389-398 (1993)
Kiyoharu HAMAGUCHI:“共享二元决策图的最优变量排序问题的复杂性”第四届国际算法与计算研讨会 (ISAAC93) 论文集。
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Kiyoharu HAMAGUCHI: "Another Look at LTL Model Checking" Proceedings of Conference on Computer-Aided Verification. 415-427 (1993)
Kiyoharu HAMAGUCHI:“LTL 模型检查的另一种看法”计算机辅助验证会议论文集。
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Yasuhiko TAKENAGA: "On the Computational Power of Binary Decision Diagrams" IEICE Trans.Inf.&Syst.E77-D. 611-618 (1994)
Yasuhiko TAKENAGA:“论二元决策图的计算能力”IEICE Trans.Inf。
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YAJIMA Shuzo其他文献
YAJIMA Shuzo的其他文献
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{{ truncateString('YAJIMA Shuzo', 18)}}的其他基金
Research on Development of Formal Logic Design Verifier for Microprocessors
微处理器形式逻辑设计验证器的开发研究
- 批准号:
07558155 - 财政年份:1995
- 资助金额:
$ 4.35万 - 项目类别:
Grant-in-Aid for Scientific Research (A)
Research on Formal Verifier of Logic Design Based on Temporal Logic
基于时态逻辑的逻辑设计形式验证器研究
- 批准号:
05558030 - 财政年份:1993
- 资助金额:
$ 4.35万 - 项目类别:
Grant-in-Aid for Developmental Scientific Research (B)
Research on Development of Logic Synthesizer and Design Verifier for Sequential Circuits Based on Boolean Function Manipulation
基于布尔函数操作的时序电路逻辑综合器和设计验证器的开发研究
- 批准号:
03555074 - 财政年份:1991
- 资助金额:
$ 4.35万 - 项目类别:
Grant-in-Aid for Developmental Scientific Research (B)
Research on Efficient Manipulation of Boolean Functions Using Shared Binary Decision Diagrams and Its Application to Computer Aided Logic Design
使用共享二元决策图有效操作布尔函数的研究及其在计算机辅助逻辑设计中的应用
- 批准号:
02452162 - 财政年份:1990
- 资助金额:
$ 4.35万 - 项目类别:
Grant-in-Aid for General Scientific Research (B)
Research on Development of a Logic Design Verification System Based on Time-Symbolic Simulation
基于时间符号仿真的逻辑设计验证系统开发研究
- 批准号:
01850074 - 财政年份:1989
- 资助金额:
$ 4.35万 - 项目类别:
Grant-in-Aid for Developmental Scientific Research (B).
Researches on the Design of Highly Reliable High-Speed Arithmetic Circuits with Redundant Coding
高可靠冗余编码高速运算电路设计研究
- 批准号:
63460134 - 财政年份:1988
- 资助金额:
$ 4.35万 - 项目类别:
Grant-in-Aid for General Scientific Research (B)
Research on Development of High-Speed Logic Simulators Using a Vector Processor and Logic Design Verification Systems
使用矢量处理器和逻辑设计验证系统的高速逻辑模拟器的开发研究
- 批准号:
61850062 - 财政年份:1986
- 资助金额:
$ 4.35万 - 项目类别:
Grant-in-Aid for Developmental Scientific Research
Research on Design of VLSI Oriented Hardware Algorithms Using Redundant Representation
采用冗余表示的面向VLSI的硬件算法设计研究
- 批准号:
60460133 - 财政年份:1985
- 资助金额:
$ 4.35万 - 项目类别:
Grant-in-Aid for General Scientific Research (B)
Developmental Research on Interactive Logic Simulator-Verifier with High-Level Hardware Description
具有高级硬件描述的交互式逻辑仿真验证器的发展研究
- 批准号:
59850059 - 财政年份:1984
- 资助金额:
$ 4.35万 - 项目类别:
Grant-in-Aid for Developmental Scientific Research
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