Research on Development of Logic Synthesizer and Design Verifier for Sequential Circuits Based on Boolean Function Manipulation

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We carried out Research on development of logic synthesizer and design verifier for sequential circuits based on Boolean function manipulation as follows:1. Logic synthesizer for sequential circuits based on Boolean function manipulationFor one-shot state assignment and single transition time assignment for asynchronous sequential circuits, we have proposed and implemented algorithms of finding minimum solutions based on Boolean function manipulation.2. Design verifier for sequential circuits based on Boolean function manipulationWe have proposed a design verification algorithm based on Boolean function manipulation, which assumes, as a specification language, branching time regular temporal logic (BRTL), which has higher expressive power as compared with the conventional temporal logics. We have developed a design verifier based on the algorithm and succeeded in design verification of microprocessors.3. Efficient Boolean function manipulationWe have clarified the theoretical properties of shared binary decision diagram (SBDD) to manipulate Boolean functions. We also have proposed and implemented an algorithm of finding input variable ordering such that the diagram becomes small and an algorithm to deal with SBDD of large size on secondary storage efficiently.4. Graphic interface of logic synthesizer and design verifierWe have implemented a multi-computer multi-screen system by using the X window system on workstations and achieved high resolution and high-speed drawing.