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Research on Development of a Logic Design Verification System Based on Time-Symbolic Simulation

基于时间符号仿真的逻辑设计验证系统开发研究

基本信息

批准号：
01850074
负责人：
YAJIMA Shuzo
金额：
$ 5.25万
依托单位：
Kyoto University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Developmental Scientific Research (B).
财政年份：
1989
资助国家：
日本
起止时间：
1989 至 1990
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-01850074/
关键词：
Logic Design Verification Timing Verification Logic Simulation Symbolic Simulation Logic Design Asynchronous Sequential Circuit Hazard 論立設計検証

项目摘要

We have carried out researches on development of a logic design verification system based on time-symbolic simulation and have got the following results.1. Algorithms for Logic Design VerificationWe have developed two methods for analyzing results obtained from time-symbolic simulation ; one is based on comparison of event-trees and the other is based on symbolic simulation of automaton that represents specification. We have also investigated the method for describing specification of digital systems using regular temporal logic.2. Algorithms for Symbolic Simulation and Boolean Function ManipulationWe have developed an efficient method for Boolean function manipulation method based on a data structure named shared binary decision diagram so as to carry out simplification and comparison of Boolean formulas which is indispensable for time-symbolic simulation.3. Implementation of a Time-Symbolic Simulation SoftwareWe have carried out researches on improvements of algorithms for simulation and result analysis of time-symbolic simulation and have implemented a time-symbolic simulator and peripheral programs that construct a logic design verification system. The simulator can handle logic circuits up to 100 gates, including ones containing feedback loops.4. Graphic Interface of the Logic Design Verification SystemWe have carried out researches on connection between workstations and a multi-computer multi-screen (MCMS) graphic system and data management, so as to develop a user interface of the logic design verification system.

我们对基于时间符号模拟的逻辑设计验证系统的开发进行了研究，取得了以下成果.逻辑设计验证的算法我们已经开发了两种方法来分析从时间符号模拟获得的结果;一种是基于事件树的比较，另一种是基于表示规格说明的自动机的符号模拟。我们还研究了用正则时序逻辑描述数字系统规范的方法.符号模拟与布尔函数操作算法我们提出了一种基于共享二叉决策图的布尔函数操作方法，实现了时间符号模拟所必需的布尔公式的化简与比较.时间符号模拟软件的实现我们对时间符号模拟的模拟算法和结果分析的改进进行了研究，并实现了一个时间符号模拟器和外围程序，构成了一个逻辑设计验证系统。该模拟器可以处理多达100门的逻辑电路，包括包含反馈回路的逻辑电路。逻辑设计验证系统的图形界面我们对工作站与多机多屏（MCMS）图形系统的连接和数据管理进行了研究，以开发逻辑设计验证系统的用户界面。