Research on Development of a Logic Design Verification System Based on Time-Symbolic Simulation

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We have carried out researches on development of a logic design verification system based on time-symbolic simulation and have got the following results.1. Algorithms for Logic Design VerificationWe have developed two methods for analyzing results obtained from time-symbolic simulation ; one is based on comparison of event-trees and the other is based on symbolic simulation of automaton that represents specification. We have also investigated the method for describing specification of digital systems using regular temporal logic.2. Algorithms for Symbolic Simulation and Boolean Function ManipulationWe have developed an efficient method for Boolean function manipulation method based on a data structure named shared binary decision diagram so as to carry out simplification and comparison of Boolean formulas which is indispensable for time-symbolic simulation.3. Implementation of a Time-Symbolic Simulation SoftwareWe have carried out researches on improvements of algorithms for simulation and result analysis of time-symbolic simulation and have implemented a time-symbolic simulator and peripheral programs that construct a logic design verification system. The simulator can handle logic circuits up to 100 gates, including ones containing feedback loops.4. Graphic Interface of the Logic Design Verification SystemWe have carried out researches on connection between workstations and a multi-computer multi-screen (MCMS) graphic system and data management, so as to develop a user interface of the logic design verification system.