Research on Design of VLSI Oriented Hardware Algorithms Using Redundant Representation
Research on Design of VLSI Oriented Hardware Algorithms Using Redundant Representation
批准号:
60460133
负责人:
YAJIMA Shuzo
金额:
$4.74万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for General Scientific Research (B)
财政年份:
1985
资助国家:
日本
项目状态:
已结题
起止时间:
1985 至 1986
中文摘要
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英文摘要
In a design and development of complex VLSI, it is very important to design its hardware algorithm first so that we can realize high performance circuit. From this point of view, we have performed researches on design of VLSI oriented hardware algorithms using redundant representation. The main results are listed below:1. Desing of Hardware Algorithms Using Redundant RepresentationWe proposed high speed hardware algorithms for elementary functions using a redundant binary representation. The redundant binary representation makes it possible to realize adder and subtracter of constant depth. By using these adder and subtracter, we have designed high speed circuits for various elementary functions.2. Design of VLSI Oriented Hardware Algorithms by Means of Sophisticated Data Expressions and Data StructuresWe have proposed an <OMICRON> (log n) depth n-bit binary division algorithm using residue number representation and designed a divider based on it. Furthermore, we proposed a high speed hardware algorithm for unification based on a new data structure named term graph.3. Redundant Coding for High Speed Hardware AlgorithmsWe have proposed redundant coding methods which makes it possible to realize constant time hardware algorithms for operations on residue class and finite Abelian group.4. Hardware Design Language Suitable for Step by Step RefinementWe have proposed a hardware design language which can describe hierarchical logic design of hardware with its hardware algorithms.
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高木直史: 電子通信学会論文誌. J69-D. 1-10 (1986)
Naofumi Takagi:电子与通信工程师协会学报 J69-D。
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通讯作者:
Naofumi Takagi: "Hardware Algorithms for Arithmetic Operations" Journal of Information Processing Society of Japan. 26. 632-639 (1985)
Naofumi Takagi:“算术运算的硬件算法”日本信息处理学会杂志。
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高木直史: 電子通信学会論文誌. J69-D. 841-847 (1986)
Naofumi Takagi:电子与通信工程师协会学报 J69-D 841-847 (1986)。
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Naofumi Takagi: "A Hardware Algorithm for Computing Sine and Cosine Using Redundant Binary Representation" The Transactions of the Institute of Electronics and Communication Engineers. J69-D. 841-847 (1986)
Naofumi Takagi:“使用冗余二进制表示计算正弦和余弦的硬件算法”电子与通信工程师学会汇刊。
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Kazuo Iwama: "Introduction to Combinatorial Algorithms" Mathematical Sciences. 285. 21-28 (1987)
Kazuo Iwama:《组合算法导论》数学科学。
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共 18 条
Research on Development of Formal Logic Design Verifier for Microprocessors
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批准号:07558155
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项目类别:Grant-in-Aid for Scientific Research (A)
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资助金额:$1.41万
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财政年份:1995
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负责人:YAJIMA Shuzo
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依托单位:
Basic Research on High-Speed Boolean Function Manipulator
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批准号:05452352
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项目类别:Grant-in-Aid for General Scientific Research (B)
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资助金额:$4.35万
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财政年份:1993
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负责人:YAJIMA Shuzo
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依托单位:
Research on Formal Verifier of Logic Design Based on Temporal Logic
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批准号:05558030
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项目类别:Grant-in-Aid for Developmental Scientific Research (B)
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资助金额:$6.85万
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财政年份:1993
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负责人:YAJIMA Shuzo
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依托单位:
Research on Development of Logic Synthesizer and Design Verifier for Sequential Circuits Based on Boolean Function Manipulation
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批准号:03555074
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项目类别:Grant-in-Aid for Developmental Scientific Research (B)
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资助金额:$5.31万
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财政年份:1991
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负责人:YAJIMA Shuzo
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依托单位:
Research on Efficient Manipulation of Boolean Functions Using Shared Binary Decision Diagrams and Its Application to Computer Aided Logic Design
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批准号:02452162
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项目类别:Grant-in-Aid for General Scientific Research (B)
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资助金额:$3.71万
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财政年份:1990
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负责人:YAJIMA Shuzo
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依托单位:
Research on Development of a Logic Design Verification System Based on Time-Symbolic Simulation
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批准号:01850074
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项目类别:Grant-in-Aid for Developmental Scientific Research (B).
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资助金额:$5.25万
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财政年份:1989
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负责人:YAJIMA Shuzo
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依托单位:
Researches on the Design of Highly Reliable High-Speed Arithmetic Circuits with Redundant Coding
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批准号:63460134
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项目类别:Grant-in-Aid for General Scientific Research (B)
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资助金额:$4.1万
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财政年份:1988
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负责人:YAJIMA Shuzo
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依托单位:
Research on Development of High-Speed Logic Simulators Using a Vector Processor and Logic Design Verification Systems
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批准号:61850062
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项目类别:Grant-in-Aid for Developmental Scientific Research
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资助金额:$4.67万
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财政年份:1986
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负责人:YAJIMA Shuzo
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依托单位:
Developmental Research on Interactive Logic Simulator-Verifier with High-Level Hardware Description
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批准号:59850059
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项目类别:Grant-in-Aid for Developmental Scientific Research
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资助金额:$4.99万
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财政年份:1984
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负责人:YAJIMA Shuzo
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依托单位: