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Research on Design of VLSI Oriented Hardware Algorithms Using Redundant Representation

采用冗余表示的面向VLSI的硬件算法设计研究

基本信息

批准号：
60460133
负责人：
YAJIMA Shuzo
金额：
$ 4.74万
依托单位：
Kyoto University
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (B)
财政年份：
1985
资助国家：
日本
起止时间：
1985 至 1986
项目状态：
已结题

项目摘要

In a design and development of complex VLSI, it is very important to design its hardware algorithm first so that we can realize high performance circuit. From this point of view, we have performed researches on design of VLSI oriented hardware algorithms using redundant representation. The main results are listed below:1. Desing of Hardware Algorithms Using Redundant RepresentationWe proposed high speed hardware algorithms for elementary functions using a redundant binary representation. The redundant binary representation makes it possible to realize adder and subtracter of constant depth. By using these adder and subtracter, we have designed high speed circuits for various elementary functions.2. Design of VLSI Oriented Hardware Algorithms by Means of Sophisticated Data Expressions and Data StructuresWe have proposed an <OMICRON> (log n) depth n-bit binary division algorithm using residue number representation and designed a divider based on it. Furthermore, we proposed a high speed hardware algorithm for unification based on a new data structure named term graph.3. Redundant Coding for High Speed Hardware AlgorithmsWe have proposed redundant coding methods which makes it possible to realize constant time hardware algorithms for operations on residue class and finite Abelian group.4. Hardware Design Language Suitable for Step by Step RefinementWe have proposed a hardware design language which can describe hierarchical logic design of hardware with its hardware algorithms.

在复杂VLSI的设计和开发中，为了实现高性能的电路，首先设计其硬件算法是非常重要的。从这一角度出发，我们开展了面向VLSI的冗余表示硬件算法设计研究。主要研究结果如下：1.基于冗余表示的硬件算法设计本文提出了基于冗余二进制表示的初等函数的高速硬件算法。冗余的二进制表示使得实现恒定深度的加法器和减法器成为可能。利用这些加法器和减法器，我们设计了各种基本功能的高速电路。利用复杂的数据表示和数据结构设计面向VLSI的硬件算法我们提出了一种基于剩余数表示的(Logn)深度n位二进制除法算法，并设计了一个基于该算法的除法器。在此基础上，提出了一种基于术语图数据结构的高速硬件合一算法。针对高速硬件算法的冗余编码，提出了冗余编码方法，实现了对剩余类运算和有限阿贝尔群运算的恒定时间硬件算法。适合逐步求精的硬件设计语言我们提出了一种能够描述硬件层次逻辑设计的硬件设计语言及其硬件算法。