Research on Development of High-Speed Logic Simulators Using a Vector Processor and Logic Design Verification Systems

点击翻译按钮获取中文摘要

For a highly reliable design of large scale logic systems, it is essential to establish rigid methodologies and efficient support systems for design verificaion. From this point of view, we habe performed researches on development of high-speed logic simulators using a vector processor and logic design verification systems. Theis main results are listed below.1. High-Speed Logic Simulators Using a Vector Processor We have developed simulation algorithms suitable for vector processing and implemented the simulators. For a zero-delay two-valued logic simulation, we have achived very high speed performance of 7.7x10^9 gate evaluation per second(combinational circuits) and 1.4x10^9 gate evaluation per second (sequential circuits). For a assignable-delay four-valued logic simulation,3.4x10^5 event per second have been achieved.2. Logic Design Verification SystemsWe have deceloped algorithms for decision problems of satisfiability and model checking of Regular Temporal Logic(RTL) which is expressively equivalent to the regular set. Based on these results, we have established design verification methods using the RTL. We have alse developed a timing verification method using #-expression, which is an extension of the regular expression.3. Workstation for Logic DesignIn order to display a large amount of information precisely and quikly, we have developed a workstation based on a multi-computer multi-screen method, which enables high-resolution display beyond the limit of a single screen and parallel high-speed drawign.