Research on Development of High-Speed Logic Simulators Using a Vector Processor and Logic Design Verification Systems

使用矢量处理器和逻辑设计验证系统的高速逻辑模拟器的开发研究

• 批准号: 61850062
• 负责人: YAJIMA Shuzo
• 金额: $ 4.67万
• 依托单位: Kyoto University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Developmental Scientific Research
• 财政年份: 1986
• 资助国家: 日本
• 起止时间: 1986 至 1987
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-61850062/
• 关键词: Logic Design Verification; Logic Simulation; Vector Processof; Temporal Logic; Specification Desctiption; Workstation; マルチスクリーン; 論理シミュレータ; 高水準ハードウェア記述; 正則時相論理; 代数的仕様記述

For a highly reliable design of large scale logic systems, it is essential to establish rigid methodologies and efficient support systems for design verificaion. From this point of view, we habe performed researches on development of high-speed logic simulators using a vector processor and logic design verification systems. Theis main results are listed below.1. High-Speed Logic Simulators Using a Vector Processor We have developed simulation algorithms suitable for vector processing and implemented the simulators. For a zero-delay two-valued logic simulation, we have achived very high speed performance of 7.7x10^9 gate evaluation per second(combinational circuits) and 1.4x10^9 gate evaluation per second (sequential circuits). For a assignable-delay four-valued logic simulation,3.4x10^5 event per second have been achieved.2. Logic Design Verification SystemsWe have deceloped algorithms for decision problems of satisfiability and model checking of Regular Temporal Logic(RTL) which is expressively equivalent to the regular set. Based on these results, we have established design verification methods using the RTL. We have alse developed a timing verification method using #-expression, which is an extension of the regular expression.3. Workstation for Logic DesignIn order to display a large amount of information precisely and quikly, we have developed a workstation based on a multi-computer multi-screen method, which enables high-resolution display beyond the limit of a single screen and parallel high-speed drawign.

为了实现大规模逻辑系统的高可靠性设计，必须建立严格的设计验证方法和有效的设计验证支持系统。从这一点出发，我们已经进行了研究的高速逻辑模拟器的开发，使用矢量处理器和逻辑设计验证系统。主要结果如下：1.使用矢量处理器的高速逻辑模拟器我们开发了适用于矢量处理的模拟算法，并实现了模拟器。对于零延迟二值逻辑仿真，我们已经实现了每秒7.7x10^9门评估（组合电路）和每秒1.4x10^9门评估（时序电路）的非常高的速度性能。对于一个可分配延迟的四值逻辑模拟，每秒可产生3.4 × 10^5个事件.逻辑设计验证系统我们给出了与正则集等价的正则时态逻辑（RTL）的可满足性判定和模型检验算法。基于这些结果，我们已经建立了使用RTL的设计验证方法。我们还开发了一种基于#-expression的时序验证方法，它是正则表达式的扩展.逻辑设计工作站为了准确、快速地显示大量的信息，我们研制了一种多机多屏方式的工作站，它能实现超越单屏限制的高分辨率显示和并行高速绘图。

项目成果

Nagisa Ishiura: Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD-87). 10-13 (1987)

Nagisa Ishiura：IEEE 国际计算机辅助设计会议 (ICCAD-87) 论文集。

Shigeharu Teshima: "Algebric Specification of Paralle Systems Based on Binary Relations between Events" Transactions of the Institute of Electronics,Information and %communication Engineers. J70-D. 19-29 (1987)

Shigeharu%20Teshima:%20"代数%20规格%20of%20Paralle%20Systems%20Based%20on%20Binary%20Relations%20Between%20Events"%20Transactions%20of%20the%20Institute%20of%20电子、信息%20和%20%communication%

Shiniji Kimura: "The Desctiption and Verification of Input Constraints and Input-Output Specifications of Logic Circuits" Transactions of the Institute of Electronics and Communication Engineers. J69-D. 502-513 (1986)

Shiniji Kimura：“逻辑电路的输入约束和输入输出规范的描述和验证”电子与通信工程师学会汇刊。

Shinji Kimura: "Formal Language Satisfying Temporal Logic Formula" Transactions of the Institute of Electronics, Information and Communication Engineers. J70-D. 10-18 (1987)

Shinji Kimura：《形式语言满足时间逻辑公式》电子、信息和通信工程师学会汇刊。

木村 晋二: 電子情報通信学会論文誌(D). J70-D. 10-18 (1987)

Shinji Kimura：电子、信息和通信工程师协会学报 (D)。10-18 (1987)。