Reconfigurable logic and Multi-bit in-memory processing with ferroelectric memristors -ReLoFeMris

考虑到边缘计算应用和物联网对电子设备的需求不断增长，从边缘到云设备的数据传输的能耗以及云中的功耗将进一步增加，除非边缘设备变得足够高效，可以直接计算传感器数据。因此，为了实现IT部门的功耗的总体降低，从而促进全球范围的CO2排放的降低，开发能够在移动的和边缘设备中实现非常高效的计算的电子技术变得越来越重要。因此，采用非易失性存储器装置的新颖计算范例受到极大关注。特别是对于嵌入式设备，执行简单的逻辑运算是有意义的，其中数据或操作数位于或生成，即在存储器中或直接在传感器节点处。近内存计算和内存计算原则上是解决数据传输操作的高能耗问题的一种方法。ReProFeMris项目致力于提供和实际实施未来的忆阻铁电技术及其在未来节能嵌入式内存处理架构中的应用。在设想的项目中要开发的忆阻铁电技术是铁电隧穿结（FTJ），其是与例如目前正在研究的经典ReRAM、STT-MRAM或PCM相比最功率有效的技术之一。 我们的项目目标是利用铁电忆阻技术的独特功能，如MLC能力和可重构逻辑的内存算术处理电路。更具体地说，我们的目标是利用铁电隧道结实现非易失性逻辑门。然而，考虑到这些器件具有极低功耗操作的巨大潜力，我们的目标是通过电路设计克服这些器件在有限MLC能力和低电流能力方面的局限性，从而利用这些概念的功能。在第一个项目周期结束时，用于极端节省面积和节能的可重新配置忆阻存储器计算电路以及MLC特征开发电路的各种基本算法构建块将在硬件中实现，并且结果将作为技术报告发布，该报告可通过NaMLab和FAU的网页公开获得。

Given the increasing demand for electronic devices in edge-computing applications and IoT, the energy consumption by data transmission from edge to cloud devices as well as the power consumption within the cloud will further increase, unless edge devices would become efficient enough to directly compute e.g. sensor date directly in places. Therefore, in order to realize an overall reduction of power consumption of the IT sector, and thus to facilitate the reduction of the world wide CO2 emission, it becomes increasingly important to develop electronic technologies that enable very efficient computing in mobile and edge devices. Therefore, novel computing paradigms that adopt non-volatile memory devices are of great interest. Especially for embedded devices it makes sense to execute simple logic operations where the data or the operands are located or are generated, namely in the memory or directly at sensor nodes. Near- and in-memory-computing is in principle an answer to the high energy costs of data transfer operations. The aspired project ReProFeMris pursuits the provision and practical implementation of future memristive ferroelectric technology and its application in future energy-efficient embedded in-memory processing architectures. The memristive ferroelectric technology that is to be exploited in the envisaged project is the ferroelectric tunneling junction (FTJ) that is one of the most power efficient technologies compared e.g. to classical ReRAM, STT-MRAM or PCM, that are under investigation at the present. Our project targets to exploit the unique features of ferroelectric memristive technology like MLC capability and reconfigurable logic for in memory arithmetic processing circuits. More specifically, we aim at the utilization of the ferroelectric tunneling junctions for the realization of non-volatile logic gates. Under consideration of the huge promises for extreme low-power operation that these devices possess, however, we target at leveraging the functionality of such concepts by overcoming the given limitations in limited MLC capability and low-current capability of these devices by means of circuit design. At the end of the first project period various basic arithmetic building blocks for extreme area-saving and energy-efficient reconfigurable memristive in-memory computing circuits as well as MLC feature exploiting circuits shall be realized in hardware and the results shall be published as a technical report which is public available via the web pages of NaMLab and FAU.