Development of Scanning Capacitance Transient Spectroscopy and Characterization of Ultrathin Oxide/Silicon Interface

在这项研究中，发展了扫描电容暂态光谱，以获得局域态和载流子寿命的空间分布。在这种方法中，可以通过扫描晶片上的非接触电极来获得晶片电特性的映射。为了验证该方法的有效性，测量了少数载流子产生寿命的晶片图。将Zerbst方法应用于非接触式表征，测量了载流子寿命的空间分布。通过与传统的零位移法进行比较，发现非接触式零位移法可以得到和传统方法一样的载流子寿命。此外，还证明了扫描电容暂态光谱可以表征载流子寿命的晶片图，并将电容-频率(C-f)方法应用于重金属污染的表征。在这项研究中，我们进行了基于C-f测量的产生寿命、界面陷阱和体陷阱的表征。以掺铜和掺金的样品为例，验证了该方法的有效性。同时，提出了一种电容-电压(C-V)法来分别表征SOI(Silicon-on-Insulator)晶片界面的界面陷阱和氧化膜中的电荷。在所提出的C-V方法中，测量了SOI-MOS电容在前栅电极和互连到后栅电极的SOI体接点之间的电容。根据SOI-MOS电容对前栅或背栅电压的依赖关系来估计相应的氧化物电荷和界面陷阱。

In this research, scanning capacitance transient spectroscopy was developed for obtaining a spatial distribution of localized states and carrier lifetime. In this method, a wafer mapping of electrical characteristics can be obtained by scanning a contactless electrode on a wafer. In order to demonstrate the validity of the developed method, a wafer map of generation lifetime of minority carriers were measured. Zerbst method was applied to the contactless characterization for the measurement of a spatial distribution of carrier lifetime. By comparison with conventional Zerbst method, it was found that the contactless Zerbst method enabled us to obtain carrier lifetime as well as the conventional method. Furthermore, it was demonstrated that a wafer mapping of carrier lifetime could be characterized by using scanning capacitance transient spectroscopy.Moreover, a capacitance-frequency (C-f) method was applied to the characterization of heavy metal contamination. In this study, the characterization of generation lifetime, interface traps, and bulk traps based on the C-f measurement was carried out. The validity of this method was assured with the use of Cu-doped and Au-doped samples.Also, a capacitance-voltage (C-V) method was proposed to separately characterize charges in respective oxide films and interface traps at the respective interfaces of SOI (Silicon-on-Insulator) wafer. In the proposed C-V method, a capacitance of SOI-MOS capacitor is measured between a front-gate electrode and SOI body contact interconnected to a back-gate electrode. The respective oxide charges and interface traps are estimated from dependence of SOI-MOS capacitance on a front-gate or a back-gate voltage.