Signal Integrity of Nano-Scale interconnect and Circuit

纳米MOSFET使大量的电路元件可以集成到一块芯片上。到目前为止，MOSFET已经根据比例方案实现了小型化，但由于要求在一块芯片上实现更多功能，芯片尺寸并没有减小；长导线的互连延迟限制了数字电路的性能。互连设计是CMOSLSI的一个永无止境的问题。对于长布线，我们开发了传输线互连(TLI)。在这个项目中，我们开发了(1)基于互连线长度分布的纳米CMOS互连资源的估计，(2)新型互连结构的建模，如周期性方案的建模，用于串扰建模的多端口分析等，(3)高达100 GHz的去嵌入方法，这是超高速纳米CMOS电路所必需的。(4)高速、低延迟、低功耗、高能效的传输线互连，已经在180 nm、90 nm和65 nm的CMOS上进行了设计、制造和评估，和小面积、低功耗、高速的片上SER/DES电路；(5)传输线、光互连和无线互连的互连性能比较。

Nano-scale MOSFET has enabled a great number of circuit elements can be integrated into a single chip. So far, MOSFET has been miniaturized according to a scaling scheme, however, the chip size has not been reduced because more functions is required to be implemented on one chip; interconnect delays of long wires limit digital circuit performance. Interconnect design is a never-ending issue with CMOS LSI. For long wiring, we have developed transmission line interconnect (TLI).In this project, we have developed (1) estimation of interconnect resource of nano-CMOS based on interconnect wire length distribution, (2) modeling of novel interconnect structure such as periodic scheme, multi-port analysis for cross-talk modeling, etc., (3) de-embedding method up to 100GHz which is essential in ultra high speed nano-CMOS circuit, (4) high-speed, low-latency, low-power, energy-efficient transmission line interconnect, which has been designed, fabricated and evaluated on 180nm, 90nm, and 65nm CMOS, and small area, low power, high-speed on-chip SER/DES circuits, (5) comparison of interconnect performance of transmission line, optical and wireless interconnects.