DEVELOPMENT OF MICROPROCESSOR ARCHITECURE DESIGN EDUCATION ENVIRONMENT

我们对微处理器设计教学环境的配置进行了研究，并开发了一个环境原型。(1)体系结构信息管理方法提出了一种适合深亚微米技术中“设计成果重用”、“面向重用设计”和体系结构设计的硬件模型FHM(Flexual Hardware Model)。在此基础上，确定了FHM数据库管理系统的规格，并开发了FHM-DBMS原型系统。最后，通过使用数字滤波器(FIR滤波器)和其他数字信号处理模块(DCT)的设计实验，对原型系统进行了评估。(2)体系结构信息的描述和输入方法首先，对体系结构信息进行分类，以便处理各种类型的处理器。然后确定了描述ARC型…所需的体系结构参数更多的高层建筑。然后，设计了一个图形用户界面，用于在设计者和系统之间输入/编辑/显示体系结构参数。(3)硬件描述的生成方法研究了处理器硬件描述语言描述的生成算法。其中一种描述适用于高速仿真，另一种适用于逻辑综合。此外，还研究了从处理器的“行为语义描述”生成硬件描述的另一种方法。(4)优化辅助环境已开发出各种体系结构级优化算法。它们中的一些能够通过考虑(A)CPU中的寄存器数量；(B)片上存储器(RAM和ROM)的数量来调整处理器的指令集来最小化应用程序的执行周期。应用程序开发环境生成器分别为标量(流水线)型和超长指令集(VLIW)型CPU核开发了编译器生成器和指令集级模拟器生成器。这些生成器接受诸如功能单元的种类和数量、寄存器的数量等体系结构参数。生成的编译器将用于性能评估以及生成的CPU核心的目标代码生成。较少

We have performed a study on the configuration of the microprocessor design education environment and developed a prototype of the environment. Major research topics performed in this research are as follows :(1) Architecture Information Management MethodA hardware model named FHM (Flexible Hardware Model) has been proposed, which is suitable for "reuse of design results", "design for reuse", and architecture design in the deep sub-micron technology. Then the specification of a database management system (DBMS) for FHM has been decided, and a prototype of FHM-DBMS has been developed. Finally, the prototype system has been evaluated through the design experiments using digital filters (FIR filters) and other digital signal processing module (DCT).(2) Description and Input Methods of Architecture InformationFirst, architecture information has been classified so that various types of processors can be handled. Then necessary architecture parameters have been identified to describe the arc … More hitecture. Next a GUI (Graphical User Interface) has been designed to input/edit/display architecture parameters between a designer and the system.(3) Generation Method of Hardware DescriptionAlgorithms to generate HDL (hardware description language) descriptions of processors have been developed. One of the yielded descriptions is suitable for high-speed simulation and the other is suitable for logic synthesis. Another approach to generate HDL description from "behavioral semantic description" of a processor was also investigated.(4) Optimization Assistant EnvironmentVarious architectural level optimization algorithms have been developed. Some of them are able to minimize execution cycles of application programs by adjusting the instruction set of the processor with consideration of (a) number of registers in CPU ; (b) amount of on-chip memories (RAM and ROM). Another algorithm is able to minimize execution cycles of VLIW (Very Long Instruction Set) type CPU core by adjusting the kinds and number of functional units.(5) Application Program Development Environment GenerationCompiler generators and instruction set level simulator generators have been developed for scalar (pipeline) type CPU and VLIW type CPU core, respectively. These generators accept architecture parameters such as kinds and number of functional units, number of registers. Yielded compilers are to be used for performance estimation as well as object code generation for the generated CPU core. Less