VLSI Implementation for Digital Video Transmission and Compression

在这个项目中，我们开发了新的视频压缩架构和用于视频传输的数字滤波器。我们还尝试基于这些架构实现vlsi。在视频压缩方面，我们开发了一种基于专用硬件组件的HDTV级MPEG2编/解码器架构。我们首先为视频编码/解码的每个过程设计一个定制的硬件模块，然后将它们与最佳配置的专用网络和内存连接起来。我们成功地将编码器/解码器功能集成在两个VLSI芯片上。对于数字滤波器，我们开发了一种针对数字滤波器定制的新型乘法算法，并将FIR实现为VLSI。该算法能够以少量硬件实现非常快的速度，利用以下事实：1)数字滤波器只有8到12位精度就足够了；2)乘数可以是常数系数，只要它是可编程的。一个11个抽头的FIR滤波器被实现为一个单芯片VLSI，工作频率为100MHz。我们还对高级综合系统进行了研究，以加快超大规模集成电路的设计。我们开发了一个由c语言编写的规范和rt级VHDL描述合成的系统，该系统可以使用现有的逻辑合成和布局工具自动转换为布局模式。

In this project, we developed new architectures for video compression and digital filters for video transmission. We also attempted to implement VLSIs based on the architectures.As for video compression, we developed an architecture for HDTV level MPEG2 encoder/decoder based on dedicated hardware components. We first designed for each process of video encoding/decoding a customized hardware module and then connect them with dedicated networks and memories which are optimally configured. We succeeded in integrating the encoder/decoder facilities on two VLSI chips.As for digital filters, we developed a novel multiplication algorithm customized for digital filters and implemented a FIR as a VLSI.The algorithm enables very fast with small amount of hardware, making use of the fact that 1) only 8 to 12 bit precision is enough for the digital filters and 2) multiplicand may be a constant coefficient as long as it is programmable. An FIR filter of 11 taps is implemented as a single chip VLSI which operates at 100MHz.We also made investigation on high-level synthesis system which expediates the design of VLSI.We developed a system which synthesizes from a specification written in C-language an RT-level VHDL description, which can be transformed automatically into layout pattern using existing logic synthesis and layout tools.