VLSI architecture for MPEG-4 Audio Visual Codec

在这个项目中，我们开发了用于无线通信的MPEG-4音频和视频压缩的新架构。我们还尝试实现基于架构的超大规模集成电路。324编/解码器，这是密切相关的MPEG-4，基于专用的硬件组件。已经专门为移动的使用设计了许多复杂的低功耗架构。263视频编解码器的一组特定的功能单元，每个单元对应一个过程，以减轻不同的性能瓶颈。723.1语音编解码器的ACELP和MP-MLQ编码方案均使用由两个MAC单元组成的紧凑型DSP核心。设计的音视频编解码器核采用0.35μ mCMOS 4LM工艺实现，共420 k个晶体管，3.3V单电源功耗为224.32mW，并实现了一个专用于便携式音频设备的MPEG-4音频解码器。根据音质评价结果，设计了各个模块的低功耗结构，如采用帧级流水线结构、优化功能数据路径等。开发了一个可重定向的编译器，用于G.723.1语音编解码器等专用DSP。

In this project, we developed new architectures for MPEG-4 audio and video compression for wireless communication. We also attempted to implement VLSIs based on the architectures. We developed an architecture for H.324 encoder/decode, which is closely related to MPEG-4, based on dedicated hardware components. A number of sophisticated low-power architectures have been devised dedicatedly for the mobile use. A set of specific functional units, each corresponding to a process of H.263 video codec, is employed to lighten different performance bottlenecks. A compact DSP core composed of two MAC units is used for both ACELP and MP-MLQ coding schemes of the G.723.1 speech codec. The designed audiovisual codec core has been implemented by using 0.35μm CMOS 4LM technology, which contains totally 420k transistors with the dissipation of 224.32mW from single 3.3V supply.Furthermore, we implementated an MPEG-4 audio decoder, which is dedicated to portable audio appliances. Based on the results of sound quality evaluation, we devise a low-power architecture for each module such as utilization of frame-level pipeline architecture, optimization of functional datapath, etc.We developed a retargetable compiler which is used for application specific DSPs, such as the G.723.1 speech codec DSP.