Modeling of Impurity Diffusion in SOI Substrates for Future LSIs

为了开发超薄SOI衬底，期望作为未来的LSI具有更高的速度和更低的功率性能，我们研究了（i）SOI中载流子浓度分布的精确测量方法，（ii）SOI的结晶质量的估计，以及SOI中杂质扩散的建模参数的提取用于工艺模拟。主要研究结果如下：（1）利用扩展电阻法测量了SOI中载流子浓度分布。对于接收的p型和n型SOI样品，在SOI和埋氧层的界面附近存在载流子耗尽（高电阻）层。在1000℃附近高温退火的样品中，p型SOI的载流子耗尽层转变为反型层，n型SOI的载流子耗尽层转变为积累层。退火过程中的变化可以通过假设埋氧层中的正电荷和界面态密度的降低来解释。(2)比较了SIMOX、UNIBOND和Eltran三种SOI材料在超薄SOI中的磷、硼扩散特性与体衬底中的扩散特性。在这样的SOI中的扩散被延迟，与体衬底相比。在超薄SOI中，SIMOX的扩散比其它SOI中的扩散慢得多。扩散延迟率被认为反映了埋氧层界面和SOI衬底的结晶质量。此外，扩散模型参数提取工艺模拟的SOI中的测量剖面。

To develop the ultra thin SOI substrates which is expected as ones for future LSIs with higher speed and lower power performance, we studied (i) the accurate measurement method of carrier concentration profiles in SOIs, and (ii) estimation of crystalline quality of SOIs, and extraction of modeling parameters of impurity diffusion in SOIs for process simulation. Results obtained are as follows :(1) Carrier concentration profiles in SOIs were measured by spreading resistance method. For as-received p-and n-type SOI samples, there is a carrier-depleted (highly resistive ) layer near the interface of SOI and buried oxide. For samples annealed at high temperatures near 1000℃, the carrier-depleted layer changes to inversion layer for p-type SOIs and to accumulation layer for n-type SOIs. The changes with annealing can be explained by assuming the positive charge in buried oxide and the decrease of interface state density.(2) Phosphorus and boron diffusion profiles in ultra thin SOIs involving SIMOX, UNIBOND and Eltran were compared with those in bulk substrates. The diffusion in such SOIs is retarded, compared with that in bulk substrates. Among ultra thin SOIs the diffusion in SIMOX is most retarded, compared with that in other SOIs. The diffusion retardation rate is considered to reflect the crystalline quality of buried oxide interface and SOI substrate. Furthermore, diffusion modeling parameters for process simulation were extracted from the measured profiles in SOI.