Study on Low Power Technologies for Next Generation Microprocessors

首先，在定量评估的基础上，构建了两类周期级仿真器：芯片多处理器仿真器和集群式超标量处理器仿真器。接下来，我们开展了两类研究：(1)系统级低功耗技术研究和(2)系统级低功耗软错误抑制技术研究。1.1)基于分支预测器的热路径检测器1.2)改进基于签名的程序阶段检测机制1.3)操作系统支持的线程级并行性动态估计1.4)片上总线串行化降低功耗1.5)片上多处理器非均匀共享缓存作为减少软错误和降低功耗的技术，我们研究了以下内容。2.1)利用水平和垂直单元的软错误缓解2.2)内容可寻址存储器上的软错误缓解2.3)针对进程异常和软错误的措施我们集成了上述技术，并展示了在下一代处理器上降低功耗和提高效率的方法。

The followings are the research products for realizing next generation low power microprocessors.First, we built up two types of cycle level simulators for the base of quantitative evaluations : the chip multiprocessor simulator and the clustered superscalar processor simulator. Next, we carried out two types of researches : (1) researches on system level low power technologies : and (2) researches on technologies for mitigating soft errors with reducing power consumption.As system level low power technologies, we studied the followings.1.1) the hot path detector exploiting branch predictors1.2) improving program phase detection mechanisms based on signatures1.3) dynamic estimation of thread level parallelism by OS support1.4) power reduction by serializing on-chip buses1.5) non-uniform shared cache on chip multiprocessorsAs technologies for mitigating soft errors with reducing power consumptions, we studied the followings.2.1) soft error mitigation exploiting horizontal and vertical parities2.2) soft error mitigation on content addressable memories2.3) measures against process anomalies and soft errorsWe integrate the above technologies and showed the methodologies for reducing power and gaining efficiency on the next generation processors.