Ferroelectrics for Nanoelectronics (FERN)

自20世纪60年代以来，硅技术的发展集中在通过小型化每18-24个月使性能和功能翻一番。现在，以几十纳米为单位测量的关键尺寸是很常见的，数十亿个由数英里长的线路连接的元件可以被封装到一个指甲盖大小的晶片上。如今，焦点正从更多的可扩展性（以英特尔创始人戈登摩尔的名字命名为更多摩尔）转向通过引入硅上的混合技术来增加功能（称为超过摩尔）。本计画研究超薄铁电材料与矽奈米电子的结合，以及其众多应用中的两个。电容是电荷随电压的变化率。这是电容器的定义性质，电容器在许多电子系统中是必需的，但相对较大。铁电体可以将电容器缩小三个数量级，因为它们的介电常数很高。不仅如此，它们的电容可以根据所施加的电压而变化，因此可以制造非常小的可调电容器，这可以在手持电子产品中找到应用，以降低功耗。如果它们能集成到硅微芯片上，将进一步节省空间。预期薄层会产生甚至更高的电容。然而，有证据表明，电容在低于50 nm时开始减小，因为据说死层在与电极的界面附近形成，但这可能是可以通过工程减少的界面效应。最近有实验证据表明，在超薄铁电薄膜中可以看到有效的负电容。如果这种材料可以被并入晶体管中，那么它将能够降低使晶体管在其导通和关断状态之间切换所需的电压（亚阈值斜率）。这将改变硅技术，允许新一代更强大的单核处理器。现代计算机具有双核或多核处理器。单核处理器会产生太多的热量，但对于许多应用来说仍然是可取的。电容对亚阈值斜率设置下限。结果是晶体管需要更大的施加电压才能导通和/或将泄漏电流，因此永远不能完全关断。这会导致功率损耗和发热增加，因为更多的晶体管被挤在同一面积的硅上，这限制了组件密度。将具有负电容的铁电膜集成到晶体管的栅极中将减小总电容，从而减小亚阈值摆幅。理解和生产高质量铁电超薄膜的需求对于这些应用中的每一个都是必要的。纽卡斯尔的原子层沉积（ALD）和帝国理工学院的脉冲激光沉积（PLD）将用于存款铁电材料钛酸钡（BTO）和钛酸锶钡（BST）薄膜。两者都允许具有原子级精度的沉积厚度。需要广泛的表征，以评估这些铁电薄膜的质量。第一原理计算机模拟将被用来获得更好的理解的电影和指导实验。沉积和热参数空间将被映射，以确定最佳的铁电性能为硅制造所规定的给定的约束。晶体管将采用最好的铁电薄膜，以确认降低亚阈值斜率。将展示集成到硅上的铁电电容器，量化每单位面积的电容增加，并检查保持高晶体管性能所需的制造限制。这还将有助于识别集成问题，其中还包括设备污染和铁电蚀刻的发展。

The evolution of silicon technology since the 1960's has focussed on doubling performance and functionality every 18-24 months through miniaturization. Critical dimensions measured in tens of nanometres are now common place and billions of components connected by miles of wiring can be packed onto a wafer no larger than a thumb nail. Today the focus is shifting away from more scaling (called more Moore after the founder of Intel, Gordon Moore) towards increasing functionality through the introduction of mixed technologies on silicon (called more than Moore). This project investigates the incorporation of ultra thin ferroelectric materials into silicon nanoelectronics and two of its many applications.Capacitance is the rate of change of charge with voltage. It is the defining property of capacitors which are necessary in many electronic systems but are relatively large. Ferroelectrics can shrink capacitors by three orders of magnitude, because their electric permittivity is so high. More than that, their capacitance can be made to vary depending on the applied voltage so very small and tunable capacitors can be made, which can find applications in hand held electronics products in order to reduce power consumption. If they could be integrated onto a silicon microchip there would be further space savings. Thin layers are expected to produce even higher capacitance. However there is evidence that capacitance starts to reduce below 50 nm as dead layers are said to form near the interface with electrodes, but this may be an interface effect which can be lessened through engineering. Recently there has been experimental evidence that effective negative capacitance can be seen in ultra-thin ferroelectric films. If such material can be incorporated into a transistor then it would be able to reduce the voltage needed to switch a transistor between its on and off states (the sub-threshold slope). This would transform silicon technology, allowing a new generation of more powerful single core processors. Modern computers have dual or multi-core processors. A single core processor would generate too much heat but is still desirable for many applications. Capacitance places a lower limit on the sub-threshold slope. The consequence is that transistors need a larger applied voltage to be on and/or will leak current and so can never be fully switch off. This leads to increased power loss and heating as more transistors are crammed onto the same area of silicon, which limits component density. Integrating a ferroelectric film with negative capacitance into the gate of a transistor would reduce the overall capacitance and thus the sub-threshold swing. The need to understand and produce high quality ferroelectric ultra-thin films is imperative for each of these applications. Atomic Layer Deposition (ALD) at Newcastle and Pulsed Laser Deposition (PLD) at Imperial College will be used to deposit thin films of the ferroelectric materials barium titanate (BTO) and barium strontium titanate (BST). Both allow deposition thicknesses with atomic level precision. Extensive characterisation is needed to assess quality of these ferroelectric films. First principles computer simulation will be used to gain a better understanding of the films and to direct experiments. The deposition and thermal parameter space will be mapped to identify best ferroelectric properties for given constraints laid down by the silicon fabrication. Transistors will be made incorporating the best ferroelectric films to confirm the reduction in sub-threshold slope. Ferroelectric capacitors integrated onto silicon will be demonstrated, quantifying the capacitance increase per unit area and examining the fabrication constraints needed to maintain high transistor performance. This will also help identify integration issues, which also include equipment contamination and the development of ferroelectric etches.