High permittivity dielectrics on Ge for end of Roadmap application

半导体行业现在主要是由大众市场消费品的应用拉动的，如果要满足对这类产品的永无止境的需求，电路性能的不断提高是至关重要的。CMOS电路或芯片内晶体管的持续小型化导致硅基MOS晶体管通道中的传输特性降低，从而降低了驱动电流，从而降低了电路速度。设计超短沟道(10纳米)完全由栅极控制的晶体管也变得越来越困难，即所谓的“短沟道效应”。为了控制后一种效应，需要越来越薄的栅电介质(约2 nm)，但这会通过量子力学隧道效应导致过多的漏电流流过栅极。这种栅极泄漏影响了晶体管的运行，最重要的是，导致了非常大的功耗，从而缩短了便携式产品中的电池寿命，还导致了芯片的严重发热。使用具有较高介电常数(K)的介质，可以在保持晶体管驱动电流的同时，获得更厚的栅氧化层，同时大大减少漏电。锗半导体被用于第一批晶体管，并具有优异的传输特性，远远优于硅的那些。首先由英特尔，其他大公司紧随其后，成功地将基于Hafnia的介质集成到MOS栅堆栈中，这有助于将一种新的激进主义引入该行业。因此，现在有相当大的兴趣将Ge pMOST和Ge或III/V材料结合在一起，用于最少的CMOS门。对于Ge来说，缺乏良好的天然氧化物的缺点现在通过沉积介质的可用性和已被证明的性质而得到缓解。GE制造的高迁移率沟道和可靠的hi-k栅电介质的组合是非常理想的。因此，该项目的中心目标是促进GE MOSFET的知识和基础科学，尤其是在栅堆叠领域。特别值得一提的是，通用电气的稀土电介质层提供了一种“神奇子弹”解决方案的可能性：在高迁移率通道上实现完全可扩展的栅极堆叠，直到“摩尔定律”所规定的cmos路线图的末尾。基于Hafnia的栅堆栈在该领域处于更先进的阶段，但需要界面层，这需要进一步研究自然氧化物(GeO2)的稳定性和表面钝化的技术解决方案。可以通过掺杂哈夫尼亚来增加K。迫切需要了解Ge晶体管开启或阈值电压背后的物理基础，这是受价带边缘附近寄生的类似受主的能态影响的，因此需要找到工程解决方案。需要开发新的测量技术来评估GE设备特有的现象。此外，几乎没有人考虑过氧化锗堆的可靠性。当然，与硅相比，有一组完全不同的问题，这反过来将对栅堆栈中合适的材料产生影响。导带边缘附近的界面态被认为是导致低电子迁移率的原因，而低电子迁移率正被证明是对大多数人的“杀手”。这些技术挑战将在这个项目中由一个团队解决，他们单独和合作，在几十年的时间里积极参与电介质学的研究。该团队涵盖了从原子水平理论和模型，到新材料和化学前体的筛选、生长和沉积、制造、物理和电子特性；到可靠性测试的主题。集团成员与这一专业链条上的工业和研究机构有着非常紧密的联系。

The semiconductor industry is now driven largely by applications pull for mass market consumer goods and it is essential that circuit performance is continually improved if the insatiable demand for such products is to be satisfied. The continuing miniaturisation of transistors within CMOS circuits or 'chips' results in degradation of transport properties in the Si-based MOS transistor channels resulting in reduced drive current and hence circuit speed. It is also increasingly difficult to engineer transistors wherein the ultra-short channel (10s of nanometre) is controlled exclusively by the gate electrode; so-called 'short channel effects'. To control this latter effect, increasingly thin gate dielectric is required (circa 2nm) but this leads to excessive leakage curent through the gate through the quantum mechanical tunnelling effect. This gate leakage compromises the operation of the transistor and most importantly, gives rise to very considerable power consumption which reduces battery lifetime in portable products, and also contributes to severe heating of the chip. The use of a dielectric with a higher permittivity (k) allows for a thicker gate oxide with much reduced leakage, whilst maintaining the drive current of the transistor.Germanium semiconductor was used for the very first transistors and possesses excellent transport properties, far superior to those of Si. The successful integration of hafnia based dielectrics for the MOS gate stack, first by Intel, closely followed by other major companies, has been instrumental in installing a new radicalism into the industry. Thus there is now considerable interest incorporating a Ge pMOST and either Ge or a III/V material for the nMOST within CMOS gates. The disadvantage of the lack of a good native oxide for the case of Ge is now mitigated by the availability and proven nature of deposited dielectrics. The combination of a high mobility channel made in Ge, and a reliable hi-k gate dielectric, is highly desirable. The central aim of this project then is to advance the knowledge and underlying science of Ge MOSFETs, crucially in the area of the gate stack. In particular, rare-earth dielectrics on Ge offer the possibility of a 'magic bullet' solution: a fully scaleable gate stack on a high mobility channel, to the end of the CMOS road map dictated by 'Moore's Law.' Hafnia-based gate stacks are at a more advanced stage in the field but require an interfacial layer which calls for further study into the stability of the native oxide (GeO2) and a technological solution for surface passivation. The 'k' can be increased by doping of the hafnia. There is a pressing need to understand the physics underlying the turn-on or threshold voltage of Ge transistors, which is affected by parasitic 'acceptor-like' energy states near the valence band edge and hence find an engineering solution. New measurement techniques need to be developed to assess phenomena peculiar to Ge devices. Furthermore, the reliability has hardly been looked at for Ge oxide stacks. There are certainly a radically different set of issues compared to Si which will have, in turn, an impact on the suitable materials in the gate stack. Interface states near the conduction band edge are thought to be responsible for the low electron mobility which is proving a 'killer' for the nMOST. These technological challenges will be addressed in this project, by a team who have individually and collaboratively, had active participation in dielectrics research over a period of decades. The team cover the subject from atomistic level theory and modelling, through screening of novel materials and chemical precursors, growth and deposition, fabrication, physical and electronic characterisation; to reliability testing. The group members have very strong links into industry and research institutions along this chain of expertise.