Reliable Numerical Computation with Parallel Unreliable Technologies

想象一下这样一个世界：医学、交通、金融和能源过程的数学动态模型，通过个性化的硬件设备，在飞行中经常被构建和完善。有了足够的计算能力，这些设备可以做出明智的决定，例如利用先进的控制技术对糖尿病患者和起搏器或除颤器进行实时干预，或者根据最新信息自动重新安排个性化的交通选择。这是一个强大的愿景，但强调了当今数字技术的许多限制，这些限制不能通过简单的技术扩展来克服，而是需要从根本上重新思考大规模并行计算的执行方式。因此，本提案的重点不在于上述任何一个重大挑战，而在于实现这场革命的基本科学问题。与将今天的技术扩展到明天的技术相比，拟议的研究可以使计算的能量/性能比提高几个数量级，在低功率计算端（复杂的个人设备）和高功率计算端（计算物理，化学，生物学和金融的进步）的当前实践中开辟了一个台阶。在接下来的十年里，计算的执行方式将会有许多根本性的转变。特别是，与使用配备数值计算单元的单个计算核心或使用此类核心的传统处理器间网络进行计算相比，两种差异正变得越来越明显。首先，如果我们允许处理技术以其可能的速度扩展，那么每个计算设备将变得越来越不可靠。其次，在相同的假设下，这种可靠性的不足将被大量并行性所补偿。独立地说，这些问题中的每一个都需要大量的研究工作来克服可靠性的缺乏和目前无法以可移植的方式有效地利用大规模并行性，并且在这些不同的快速发展的领域有许多正在进行的国际研究。然而，这些看似不同的挑战有一个尚未开发的共同研究核心。数值计算中的大规模并行性要求一种有效处理计算中的数值不精确的方法，即使在完全可靠的电路中也是如此。人们心中必须有一个可容忍的数值精度的说明。一旦这样的规范存在，并且可以形式化，它就打开了使用该规范作为强大的专业优化编译器的输入的潜力，能够优化数值硬件和软件，以便在给定的功率范围内实现具有最大性能的规范。未来设备可靠性的缺乏将传播到数值计算中，成为硬件中明显的数值误差。克服这些错误的一种方法是以某种冗余方式利用并行性。一种激进的替代方法是在已经要求的公差规格范围内“隐藏”由不可靠部件引起的数值误差。对于一个固定的硅区域，计算硬件中新兴的多核革命带来了数值精度和计算性能之间的紧张关系；人们不能再为过度设计的硬件在性能上付出代价。因此，这项研究的核心将是发展数学技术来推理将数值软件编译成并行硬件，扩大对一般非线性和控制密集型算法的适用性，要求应用非线性系统理论来推理数值摄动下算法类的收敛性，以及机械化代数方法来推理数值算法的准确性。

Imagine a world where mathematical dynamical models of processes in medicine, transport, finance and energy, are routinely constructed and refined, on the fly, by personalised hardware devices. With sufficient computational power, such devices could make intelligent decisions, for example utilising advanced control techniques for real-time intervention in diabetic patients and for pacemakers or defibrilators, or to automatically re-route personalised transport options based on up-to-the-minute information. The vision is a powerful one, but highlights many limitations of today's digital technologies, limitations that will not be overcome with simple scaling of technology, but which need a fundamental rethink of the way in which massively parallel computation can be performed. The focus of this proposal is therefore not on any one of the above grand challenges, but rather on the fundamental scientific problems enabling this revolution. The proposed research could enable computation at orders of magnitude better energy/performance ratio than would be possible by extending today's techniques to tomorrow's technologies, opening up a step change in current practices at both the low power end of computation (sophisticated personal devices) and the high power end (advancements in computational physics, chemistry, biology and finance).Over the next decade, there will be a number of radical shifts to the way in which computation is performed. In particular, rather than computing with a single computational core equipped with a numerical computational unit, or with a traditional inter-processor network of such cores, two differences are becoming increasingly apparent. Firstly, if we allow process technology to scale at the rate it could, then each computational device will become increasingly unreliable. Secondly, under the same assumption, this lack of reliability will be compensated by massive parallelism. Independently, each of these issues requires considerable research effort to overcome the lack of reliability and the current inability to make efficient use of massive parallelism in a portable manner, and there is much ongoing international research in these distinct fast-moving areas.These seemingly distinct challenges, however, have an untapped common research core. Massive parallelism in numerical computation mandates a way to effectively deal with numerical imprecision in computation, even in fully reliable circuitry. One must have in mind a specification of tolerable numerical accuracy. Once such a specification exists, and can be formalised, it opens up the potential to use this specification as input to a powerful specialised optimising compiler, capable of optimising numerical hardware and software in order to achieve the specification with maximum performance within a given power envelope. Lack of reliability in future devices will propagate to numerical computation as noticeable numerical errors in the hardware. One way of overcoming these errors is to utilise parallelism in some kind of redundant fashion. A radical alternative is to `hide' the numerical errors caused by unreliable components within the tolerance specification already required. For a fixed silicon area, the emerging multi-core revolution in computational hardware brings to the fore a tension between numerical precision and computational performance; one can no longer afford to pay the price in performance for over-designed hardware.At the core of this research will therefore be the development of mathematical techniques to reason about the compilation of numerical software into parallel hardware, broadening applicability to general classes of nonlinear and control-intensive algorithms, requiring the application of nonlinear systems theory to reason about the convergence of classes of algorithm under numerical perturbation, and mechanising algebraic approaches to reasoning about accuracy in numerical algorithms.