Yield and reliability enhancement techniques for novel memory devices

用简单的术语描述拟议的研究，以便向普通观众宣传[最多4000个字符]。请注意，如果获得资助，此摘要将自动发布在EPSRC的网站上。最近开发的基于连续可变器件的存储器架构，如相位电荷存储器，可编程金属化单元或忆阻器，其可靠性问题与影响CMOS存储器的问题截然不同。这些新的存储器虽然基于不同的技术，但它们都共享存储信息的原理，即施加到连续可变设备的电阻值，因此也可能发生的故障类型。本项目建议利用从实验结果中获得的数据来表征连续可变设备，并利用信息和架构冗余来提高这些设备的可靠性和产量。为了面对大量缺陷的存在，将使用合适的备用资源（诸如备用行和/或列）与合适的错误检测方法和有效的重编址方案组合来替换故障元件。为了利用备用资源的使用，代码新的模型和算法来估计的可靠性与开销的权衡将开发，与获得这些存储器设备的可靠性感知驱动的合成工具的目的。

Describe the proposed research in simple terms in a way that could be publicised to a general audience [up to 4000 chars]. Note that this summary will be automatically published on EPSRC's website in the event that a grant is awarded.The recently developed memory architectures based on resistive-variable devices such as Phase Charge Memories, Programmable Metallization Cell or memristors have reliability issues that are drastically different from those affecting CMOS based memories. These novel memories although based on different technologies, they all share the principle of storing information as the resistance value imposed to a resistive-variable devices and consequently also the possible type of faults that may occur.This project proposes to leverage data obtained from experimental results to characterize resistive-variable devices and to exploit both information and architectural redundancies to enhance reliability and yield of these devices. To face the presence of a massive number of defects suitable spare resources, such as spare row and/or columns will be used combined with suitable error detection methods and efficient readdressing scheme to substitute faulty elements. To leverage the use of spares resources, codes novel models and algorithms to estimate the reliability versus overhead trade-off will be developed, with the aim of obtaining a reliability-aware driven synthesis tool for these memory devices.