Low-Dimensional Electronic Device Fabrication at Low Cost over Large Areas

有一个普遍的经验法则，精度每提高十倍，制造成本就会翻一番。粗略地说，这就是为什么建立一个制造微处理器的工厂要花费数十亿英镑，其中被制造的晶体管的物理尺寸在几纳米的长度范围内，而建立一个设施来制造印刷电路板的成本足够便宜，可以广泛使用，但特征是数百微米的规模。有些情况下，这一规则可以被打破。其一是使用自然形成于纳米尺度上的低维材料。石墨烯就是一个例子，近年来它受到了很大的关注。它自然形成一个碳原子的二维薄片，因此不需要经过加工就能达到纳米级的厚度。这种自下而上的过程以非常低的成本实现了高分辨率，这是人们感兴趣的原因之一。然而，它们仍然需要与材料进行电接触才能定义一个完整的装置。理想情况下，我们只想使用少量的此类材料，例如，通过在纳米间隙内使用低维材料(例如石墨烯)来图案化两个相隔仅几纳米的金属电极。由于如此长的金属尺寸的图案化需要高分辨率工艺，成本再次变得令人望而却步。该项目旨在直接解决这一制造问题，方法是将一种名为粘合光刻的新兴技术与低维材料的生长相结合，创建使用这些材料制造真正电子设备所需的结构。粘合光刻使用自组装单分子膜(SAM)来控制不同材料之间的粘合程度。这使得一种金属可以沉积在低成本的衬底上，如塑料，并使用低成本、低分辨率的工艺进行图案制作，第二种金属可以沉积在顶部的各处。使用SAM，可以确保第二种金属不会粘住第一种金属。这使得第二种金属可以从第一种金属中剥离出来，在加工过程中将其暴露出来，并在第一种金属的边缘周围留下一个纳米间隙。因此，一种纳米级的结构被制造出来，但没有相关的成本。剥离过程已经被证明是实现这一工作的关键。因此，该项目旨在设计和制造一种低成本的工具，在10x10厘米长的范围内执行这种剥离过程，但有一条明确的路线可以扩大到大范围(例如A3纸)。此外，我们还将展示，NanoGap可以与低维材料的沉积结合在一起，创建真正的电子纳米级设备，但成本要大得多。我们预计，这将允许为从逻辑到存储器再到传感器的整个范围的应用开发全新的设备。

There is a general rule of thumb that the cost of manufacturing doubles every time the precision is improved by a factor of ten. Crudely, this is why it costs billions of pounds to set up a fabrication plant to manufacture microprocessors, where the physical size of the transistors being manufactured is on the length scale of a few nanometre, compared with the cost of setting up a facility to manufacture printed circuit boards which sufficiently cheap to be widely available, but features are on the scale of hundreds of micrometers.There are cases of where this rule can be broken. One is in the use of low-dimensional materials which naturally form on a nanometre length scale. An example of this is graphene, which has received a lot of attention in recent years. It naturally forms in a two-dimensional sheet of carbon atoms, and so does not need to be 'machined' to achieve a nanometre-scale thickness. Such 'bottom-up' processes achieve high resolution at very low cost, which is one reason for the interest. However, they still require electrical contacts to be made to the materials to define a complete device. Ideally, we would like to use only a small quantity of these materials, for example by patterning two metal electrodes separated by only a few nanometre with the low-dimensional material (e.g. graphene) inside the nanogap. As the patterning of the metal one this length scale requires a high resolution process, the cost becomes prohibitive again.This project aims to tackle this manufacturing problem directly by combining an emerging technique called 'adhesion lithography' with the growth of low-dimensional materials to create the structures required to make real electronic devices using these materials. Adhesion lithography uses self-assembled monolayers (SAM) to control how well different materials can stick to each other. This allows one metal to be deposited onto a low-cost substrate, like plastic, and patterned using a low cost, low resolution process and a second to be deposited everywhere over the top. Using the SAM, it is possible to ensure that the second metal does not stick to the first. This allows the second metal to be peeled away from the first, uncovering it in the process and leaving a nanogap all around the edge of the first metal. A nanometre scale structure hastherefore been manufactured, but without the associated cost.The peeling process has been shown to be critical to make this work. Therefore, this project aims to design and build a low cost tool to carry out this peeling process on a 10x10 cm length scale, but with a clear route to scaling up to large areas (e.g. an A3 sheet). In addition, we will show that the nanogap can be incorporated with the deposition of a low-dimensional material to create a genuine electronic nanoscale device, but with the cost of a much larger device. We expect the this will allow entirely new devices to be developed for a whole range of applications, from logic to memories to sensors.