Direct Writing of Nanodevices: A Sustainable Route to Nanofabrication
Direct Writing of Nanodevices: A Sustainable Route to Nanofabrication
批准号:
EP/X016404/1
负责人:
David Lewis
金额:
$179.15万
依托单位:
依托单位国家:
英国
项目类别:
Research Grant
财政年份:
2023
资助国家:
英国
项目状态:
未结题
起止时间:
2023 至 --
中文摘要
利用光刻技术在纳米尺度上书写结构的能力支撑着现代社会。我们认为理所当然的电子设备包含集成电路(IC),而这些电路的关键部件是场效应晶体管(FET)。四十多年来,根据“摩尔定律”,它们的体积每两年缩小一倍。电子行业的路线图现在假设这种不断缩小的规模将持续下去-至少到21世纪20年代中期。2019年底,极紫外光刻(EUVL)开始用于制造FinFET(即类似于鳍的FET),作为7 nm节点IC的一部分。不幸的是,EUVL具有天文数字的成本,其中每个工具的成本> 1亿美元,并且维护成本也类似。显然,这对于较大的半导体制造商,即Intel、TSMC、Samsung、Global Foundries、Infineon、LG来说是巨大的投资。成本是不可持续的,这导致国际半导体技术路线图(ITRS)宣布将FET器件尺寸减小到超过5 nm节点在经济上不再可行。这导致了半导体行业未来发展方向的重大不确定性,尤其是对于那些面临被市场淘汰风险的小型制造商。此外,光刻是一种减成法并且非常需要能量。在制造过程中添加层,然后在制造过程中大部分被蚀刻掉。这是一种浪费,需要更可持续的进程向前推进。同样,用于将光刻结构转移到衬底(硅或化合物半导体)中的步骤的等离子体蚀刻使用大量能量。如果我们可以直接写入结构,我们将使用更少的前体,产生更少的废物,减少能源消耗,并可能使该过程可持续发展,并为较小的制造商所用。在本提案中,我们将展示一种新的可持续且相对廉价的制造工艺,该工艺将减少浪费,降低能耗,并可能使该工艺可持续发展,并可供英国及其他地区的小型制造商使用。这种新的制造技术是基于分子前体分子在离子束中的分解。由于这些前体具有预先形成的金属-硫族元素键,它们在离子束中直接分解成有用的半导体,例如金属氧化物和金属硫化物,具有超过7 nm节点的写入图案分辨率,与半导体工业中的现有工艺相比,时间和处理成本仅为一小部分。我们将证明,一些有用的纳米级器件(i)热电能发电(ii)单光子检测77 K以上和(iii)逻辑电路的16位存储器可以用这种方式准备,写在决议超出了目前可能的大多数小型半导体企业在英国。这项工作是国家的重要和非常及时的;大约13个六次方(10 e22)晶体管已经由光刻制成。例如,新智能手机中有85亿个FET,全球约有35亿部智能手机。对于英国来说,要在下一代7纳米器件中竞争,我们需要创新和可持续的方法;我们没有足够大的公司投资EUV写入工具。(例如:我们没有一个相当于全球代工厂,三星,台积电,或英特尔),以领导英国在这一领域的活动,而不解决关键技术支撑工具的这一缺陷将意味着英国在新兴技术方面严重落后。通过为这一提议提供资金,英国可以开始解决其制造能力的这一赤字。
英文摘要
The ability to write structures at the nanoscale using lithography underpins modern society. The electronic devices we take for granted contain integrated circuits (ICs), and the key component of those circuits are field-effect transistors (FETs). They have reduced in size by a factor of two every two years for over forty years, following "Moore's Law". The roadmap for the electronics industry now assumes that this constant reduction of size will continue - at least until the mid-2020s. At the end of 2019, Extreme ultraviolet lithography (EUVL) began to be used to manufacture FinFETs (i.e. FETs that resemble a Fin) as part of ICs at the 7 nm node. Unfortunately, EUVL has an astronomical cost, where each tool costs > $100 M dollars with similarly costs for maintenance. It is evident that this is a colossal investment for larger' semiconductor manufacturers i.e. Intel, TSMC, Samsung, Global Foundries, Infineon, LG. The cost is not sustainable which has led the International Technology Roadmap for Semiconductors (ITRS) to declare that it will no longer be economically feasible to decrease FET device dimensions past the 5 nm node. This has led to significant uncertainty in the future direction of the semiconductor industry, especially for smaller manufacturers that risk being priced out of the market. Additionally, lithography is a subtractive process and very energy demanding. Layers are added in manufacture that are then largely etched away during fabrication. This is wasteful and more sustainable processes are needed moving forward. Equally, plasma etching for the step where the lithographed structure is transferred into the substrate (silicon or compound semiconductor) uses a large amount of energy. If we could directly write structures we would use less precursor, produce less waste and reduce energy consumption and potentially make the process sustainable as well as accessible for smaller manufacturers. In this proposal, we will demonstrate a new sustainable and relatively inexpensive manufacturing process that will allow less waste and reduce energy consumption and potentially make the process sustainable as well as accessible for smaller manufacturers in the UK and beyond. This new manufacturing technique is based on the decomposition of molecular precursor molecules in ion beams. As these precursors have preformed metal-chalcogen bonds they decompose in the ion beam directly to useful semiconductors such as metal oxides and metal sulfides, with written pattern resolutions beyond the 7 nm node, at a fraction of the time and processing cost compared to extant processes in the semiconductor industry. We will demonstrate that a number of useful nanoscale devices for (i) thermoelectric energy generation (ii) single photon detection above 77K and (iii) logic circuits for 16 bit memory can be prepared in this way, written at resolutions beyond what is currently possible to most small semiconductor businesses in the UK. This work is nationally important and extremely timely; approximately 13 sextillion (10e22) transistors have been made by lithography. For example, there are 8.5 billion FETs in a new smartphone and around 3.5 billion smartphones on the planet. For the UK to compete in the next generation of devices at the 7 nm node we need innovative and sustainable approaches; we do not have companies large enough to invest in EUV writing tools (for example: we do not have an equivalent to Global Foundries, Samsung, TSMC, or Intel) to lead UK activity in this area, and to not address this deficiency in a key technological underpinning tool would mean the UK falling behind significantly in emerging technologies. By funding this proposal the UK can begin to address this deficit in its manufacturing capability.
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