Conduit Diffusion in Silicon on Silicide on Insulator substrates

绝缘体上硅(SOI)技术对未来几代集成电路芯片至关重要。SOI提供了潜在的更快的芯片操作、简化的制造技术和低功耗操作。它还提供了在一块芯片上集成整个电子系统的可能性。在这种相对简单的衬底上，出现了非常新颖的变体。绝缘体上硅化物衬底(SSOI)就是这样一种衬底。该衬底包括埋在有源硅下面的低阻层(硅化钨)。这一层的主要应用将是欧姆接触和返回到表面接触之前的电流的横向流动。IC使用埋离子注入层来实现这一功能，但硅化物在串联电阻方面提供了两个数量级的减少。因此，采用这种衬底可以大大降低双极型和功率器件中的寄生电阻。SSOI还提供了尚未开发的潜在优势。埋在地下的硅化物是多晶结构，因此硅的常见掺杂扩散将是通过晶界扩散，这将是快速的。可以使用低热预算处理来将这些掺杂剂移动相对较远的距离，而不干扰覆盖硅中的其他掺杂剂轮廓。然后，可以采用短时间快速热退火来从硅化物中取出扩散掺杂，以在硅中产生超浅结。这一切都可以在器件生产的近后端实现，确保严格控制所有结型材，消除广泛埋入的植入层，并简化制造时间表。这项技术将为激动人心的新工艺和设备架构提供进一步的机会，在从IC和微波设备到功率和智能功率晶体管的各种频谱上，在单位成本和电子设备性能方面具有优势。因此，本合同的重点是对硅化钨中的掺杂扩散进行详细的科学调查。将使用灵敏的电子实验结构，这将允许准确地描述掺杂剂在距离上的扩散。这对提供扩散系数数据、分离系数等非常重要，这些数据将使未来的工艺和设备设计成为可能。还必须制定向埋藏的硅化物层供应掺杂剂的策略。对于近后端的加工技术，这将需要重新灌装的沟槽技术的变化。这个项目将寻求使用一些重新填充材料来研究这种方法。这项技术将带来超低的寄生阻力。因此，确保任何沟槽填充技术都可以提供低附加阻力是适当的。因此，将采用钨重新填充沟槽，为功率器件和线性IC提供优化的基板。这项技术的潜力将通过一个相对简单的微波二极管来展示。该二极管将在SSOI衬底上制造，并将表现出最小的寄生电容和电阻。在项目期间，可以在新的合同或行业合作中开发基板和拟议的技术，以解决智能功率/垂直功率设备、线性IC技术和高频部件。

Silicon on Insulator (SOI) technology is now of critical importance to future generations of integrated circuit chips. SOI offers potentially faster chip operation, simplified manufacturing technology and low power operation. It also offers the possibility of integrating entire electronic systems on a chip. Very novel variations on this relatively simple substrate are emerging. The Silicon on Silicide on Insulator (SSOI) substrate is one such substrate. This substrate includes a low resistivity layer (tungsten silicide) buried under the active silicon. Primary applications of this layer would be as ohmic contacts and for lateral current flow of current prior to return to surface contacts. ICs use buried ion implanted layers for this function but the silicide offers 2 orders of magnitude reduction in series resistance. Parasitic resistance in bipolar and power devices can therefore be substantially reduced by employing this substrate. The SSOI offers further potential advantage which has not yet been exploited. The buried silicide is polycrystalline in structure and diffusion of common dopants for silicon will therefore be by grain boundary diffusion which will be rapid. Low thermal budget treatment may be used to move these dopants relatively long distance without disturbance of other dopant profiles in the overlying silicon. Short time rapid thermal anneal can then be employed to out diffuse dopant from the silicide to produce ultra-shallow junctions in the silicon. This can all be achieved at the near back end of the device production ensuring tight control of all junction profiles, elimination of wide buried implanted layers and simplification in the manufacturing schedule. This technology will provide further opportunity for exciting new process and device architectures with advantage offered in unit cost and electronic device performance over the spectrum from ICs and microwave devices to power and smart power transistors. The focus of this contract is therefore to conduct a detailed scientific investigation of dopant diffusion in tungsten silicide. Sensitive electronic experimental structures will be employed which will allow accurate characterisation of dopant diffusion over distance. This is vitally important to provide the diffusivity data, segregation coefficients etc which will allow design of future processes and devices. Strategy for supply of dopant to the buried silicide layer must also be developed. For near back end of processing technology this will require variations on refilled trench technology. This project will seek to investigate this approach using a number of refill materials. The technology will lead to ultra low parasitic resistance. It is therefore proper to ensure that any trench refill technology may offer low additional resistance. Trench refill with tungsten will therefore be undertaken to provide an optimised substrate for power devices and linear ICs. The potential of the technology will be demonstrated with a relatively simple microwave diode. The diode will be manufactured on the SSOI substrate and will exhibit minimised parasitic capacitance and resistance. Exploitation of the substrate and the proposed technology can develop in new contracts or industrial collaborations during the time of the project to address smart power/ vertical power devices, linear IC technology and high frequency components.