Energy Efficient Networks-on-Chip for Dynamically Reconfigurable Computing Platforms.

这项工作的目的是研究一种片上网络结构，它将使未来的可重构计算系统集成数十或数百个实现嵌入式微处理器、知识产权核心、可重构结构、专用本地存储器和DSP功能的处理块。可重新配置的NoC结构将指导多个处理块之间的有效通信和数据交换，并实现容错和非常高的通信带宽，具有低延迟和低能耗。处理块将根据应用程序需求改变其功能和操作点。

The purpose of this work is to investigate an on-chip network fabric that will enable future reconfigurable computing systems integrating tens or hundreds of processing tiles implementing embedded microprocessors, intellectual property cores, reconfigurable fabrics, dedicated local memories and DSP functionality. The reconfigurable NoC fabric will direct the effective communication and exchange of data among the multiple processing tiles and enable fault-tolerance and very high communication bandwidths with low-latency and low energy consumption. The processing tiles will morph their functionality and operation point based on the application demands.