Secure Design Flow

安全在支付和访问控制设施等传统应用中的重要性正在迅速增长，在无线计算中也是如此。手机、机顶盒、掌上电脑、心脏监测器、闹钟。许多电子公司在安全增强设备的生产上投入了大量资金。例如，正如最近的出版物所显示的那样，许多专门从事智能卡的国际公司对电路级安全领域有着浓厚的兴趣。该项目的总体目标是开发一套设计方法和工具，在使用基于高基优化技术的解决方案为安全系统开发硬件的背景下，增强工业EDA工具的使用。在这个项目中，我们希望探索更广泛的解决方案，包括伽罗瓦油田。我们将研究用于功率平衡和容错的高阶基(使用n取1码、m取n码)的直接编码的新方法，并开发围绕它的综合流程。增强的语言驱动的设计流程应该结合某些功耗效率和面积效率高的同步和异步技术以及相关的低功耗多值逻辑映射技术。新的流程不会为整个系统规定特定的架构风格或综合风格。因此，该项目的目标是一套从根本上改进的设计方法和有效的工具支持，用于根据常见HDL的行为描述来构建用于安全应用的电路，例如智能卡IC。该方法将包括将高基技术应用于安全电路开发的措施，以增强功率平衡签名和防止故障插入的保护。这将包括使用延迟不敏感代码和代码平衡等技术。这项工作的主要贡献将是：(1)在结构级别上，在更高的基数级别(使用n中1，n中m代码)开发了一组RTL体系结构，主要针对低功耗、功率平衡和容错实现，满足一系列面积、速度、功率平衡和故障诱导检测的权衡，并由组件库支持；(2)在行为级，基于高基可扩展体系结构的完整安全设计流程，其中功率平衡和容错方面可以被从HDL转换为高效控制、数据路径和接口逻辑的工具所结合和支持。(1)的结果将用作基本构建块，与当前设计实践中已经使用的构建块一起使用。同时，(2)项下的项目将服务于增强当前设计流程的目标，即从行为安全描述开始，目标是更高效的高基电路实现。该项目将涉及与主要智能卡公司Atmel的合作，后者将在实验前线提供支持，并获得重要的案例研究。

The importance of security is rapidly growing in traditional applications, such as payment and access control facilities, as well as in wireless computing, viz. mobile phones, set top boxes, PDA, heart monitors, alarms. Many electronics companies put large investments into the production of security-enhanced devices. For example, many international companies specialising in smart cards have strong interests in the area of circuit level security, as recent publication show.The overall aim of this project is to develop a set of design methods and tools for enhancing the use of industrial EDA tools in the context of developing hardware for secure systems using solutions that are based on higher radix optimization techniques. In this project we wish to explore a much broader range of solutions encompassing Galois Fields. We will study new methods for direct encoding in higher radices (using 1-of-n, m-of-n codes) for power-balancing and fault-tolerance and develop the synthesis flow around it. The enhanced language driven design flow should incorporate certain power efficient and area efficient synchronous and asynchronous techniques together with relevant low-power multi-valued logic mapping techniques. The new flow would not stipulate a specific architectural style or synthesis style for the entire system. In this way, our new approach could be characterised as the 'best-effort' design and synthesis of efficient secure logic at the asynchronous or synchronous level.The goal of the project, therefore, is a set of radically improved design methods and efficient tool support for constructing circuits for secure applications, such as smart card ICs, from behavioural descriptions in common HDLs, such as Verilog, VHDL, SystemC etc. The methodology will incorporate measures for applying higher-radix techniques to the development of secure circuits for enhancing power-balanced signatures and protection against fault-insertion. This will include the use of techniques such as delay-insensitive codes and code balancing.The key contributions of this work will be: (1) at the structural level, a set of RTL architectures developed at the higher radix level (using 1-of-n, m-of-n codes), primarily targetting low power, power-balanced and fault tolerant implementations, meeting a range of area, speed, power-balancing and fault-induction detection tradeoffs and supported by component libraries; (2) at the behavioural level, a complete security design flow based on higher radix scalable architectures, in which power-balancing and fault-tolerant aspects can be incorporated and supported by tools for translating from the HDLs into efficient control, datapath and interface logic. The results of (1) will be used as base building blocks to be used together with those that are already used in the current design practice. At the same time those under (2) will serve the goal of enhancing the current design flow, i.e. starting from the behavioural security descriptions and targetting more efficient higher-radix circuit implementations.The project will involve collaboration with a major smartcard company Atmel who will provide support on the experimental front and access to important case studies.