DEVELOPMENT OF EMBEDDED CONTROLS FOR PULSED & FT ESR

这个子项目是许多研究子项目中利用 资源由NIH/NCRR资助的中心拨款提供。子项目和 调查员(PI)可能从NIH的另一个来源获得了主要资金， 并因此可以在其他清晰的条目中表示。列出的机构是 该中心不一定是调查人员的机构。 脉冲和FT-ESR光谱实时控制(RTC)系统开发的第二个里程碑最近过去了。该系统包括脉冲ESR光谱仪计时系统所需的所有基本功能，成本低于2,500美元。这个系统比以前的版本先进得多。它具有体积小、功耗低的特点。实时时钟容量由我们设计的基于SHARC DSP的处理器板提供，该处理器板通过专有的160MB/S总线协调多个硬件卡的功能。所有卡都是在Acert使用表面贴装技术设计和制造的多层印刷电路板。最新版本可以提供高达8个脉冲的脉冲序列，以高达500 kHz的重复频率进行相位循环。脉冲序列可以在10-20微秒内更新，因此能够快速扫描，仅限于驻留在PC主机中的数字化仪。目前，上位机与DSP之间的通信是基于RS232接口的。USB2.0或专有的串行高速链路正在开发中。我们未来的计划是使用ADI公司的更快的DSP处理器和配套的FPGA来消除DSP中的一些控制任务，然后它将负责控制脉冲序列时序并与AP240中的数据捕获过程同步。将增加DSP存储器，以保存脉冲序列的每个时间步长的精细调整。光谱仪的控制是基于用Visual C++编写的图形用户界面。AP240的定制功能提供外部控制线，用于在加法和减法之间切换。这一功能将使我们在未来的工作中，能够在20ms内捕获整个2D-Eldor信号，并根据蛋白质折叠的停流和连续流实验的需要实时积累它。

This subproject is one of many research subprojects utilizing the resources provided by a Center grant funded by NIH/NCRR. The subproject and investigator (PI) may have received primary funding from another NIH source, and thus could be represented in other CRISP entries. The institution listed is for the Center, which is not necessarily the institution for the investigator. The second milestone in the development of a real-time control (RTC) system for pulsed and FT-ESR spectroscopy was recently passed. The system comprises all basic features required for a pulsed ESR spectrometer timing system with a cost of under $2,500. This system is much more advanced compared to earlier versions. It features small size and low power consumption. RTC capacity is provided by a processor board of our design based on SHARC DSP, which coordinates the functions of several hardware cards via a proprietary 160 MB/s bus. All cards are multi-layer PCBs designed and fabricated at ACERT using surface-mount technology. The latest version can supply pulse sequences of up to 8 pulses with phase cycling at repetition rates of up to 500 kHz. The pulse sequence can update in 10-20 microseconds, and is thus capable of fast sweeps limited only by the digitizer residing in the PC host. Currently, communication between the host PC and the DSP is based on the RS232 interface. A USB2.0 or proprietary serial high-speed link is under development. Our future plans are to use a faster DSP processor from Analog Device with companion FPGA to remove some control tasks from the DSP, which will then be tasked with control over pulse sequence timing and synchronization with the data capture process in AP240. The DSP memory will be increased to hold fine adjustments for every time step of the pulse sequence. Spectrometer control is based on a GUI written in Visual C++. A custom feature of the AP240 provides external control lines for switching between addition and subtraction. This feature will allow us in future work to capture the whole 2D-ELDOR signal in 20 ms and accumulate it in real time as required in stop-flow and continuous flow experiments on protein folding.