NANOSECOND RADIOFREQUENCY SWITCH DRIVER DESIGN UPGRADE & HYBRIDIZATION

这个子项目是许多利用资源的研究子项目之一 由NIH/NCRR资助的中心拨款提供。子项目的主要支持 而子项目的主要调查员可能是由其他来源提供的， 包括其它NIH来源。 列出的子项目总成本可能 代表子项目使用的中心基础设施的估计数量， 而不是由NCRR赠款提供给子项目或子项目工作人员的直接资金。 改进的射频（r.f.）快速切换在ACERT下一代脉冲ESR光谱仪的设计中，通过PIN二极管开关提供能量对于接收器保护和死区时间减少至关重要。用于PIN开关的新型专用电子驱动器的制造先前已在Freed Research Group内完成（美国专利#5，214，315）。本发明的一个独特的特征是，它优化了在Si和GaAs PIN二极管阵列典型的反应负载条件下的转变速度。我们目前正在升级驱动器，建模和指定更高性能的功率MOSFET半导体，并将开关驱动器重新格式化为高性能混合电路。将包括开关驱动器的分立元件集成到紧凑的陶瓷基板上将通过最小化与电路互连相关联的寄生电感来显著提高开关速度。我们正在采用先进的商业软件工具，以准确地模拟高阶互连寄生效应和半导体特性;这种能力允许有效的模拟和选择最适合这种应用的新半导体。它还允许准确预测微小寄生电抗的大小和影响，大大减少了布局变化收敛所需的时间。 模拟研究表明，最新的混合驱动器设计应执行在6 - 8 ns的水平为15-20 nC的电荷转移。这个数字转换为可能的r.f.对于高功率硅PIN二极管阵列，开关速度在10 - 14 ns范围内，或者对于高电压GaAs PIN阵列，开关速度在4 - 6 ns范围内。驱动器混合组件物理上很小，因此可以靠近其相关联的PIN阵列，从而最小化有害的传输线效应和电磁干扰。我们正在评估进一步的候选人PIN器件，并计划requisiton的混合驱动器，一旦PIN二极管已经在我们正在进行的微波光谱仪的发展的背景下，其特征。

This subproject is one of many research subprojects utilizing the resources provided by a Center grant funded by NIH/NCRR. Primary support for the subproject and the subproject's principal investigator may have been provided by other sources, including other NIH sources. The Total Cost listed for the subproject likely represents the estimated amount of Center infrastructure utilized by the subproject, not direct funding provided by the NCRR grant to the subproject or subproject staff. Improved fast switching of radiofrequency (r.f.) energy via PIN-diode switches is essential for receiver protection and deadtime reduction in the design of ACERT next-generation pulsed-ESR spectrometers. Fabrication of a novel, specialized electronic driver for PIN switches has previously been accomplished within the Freed Research Group (U.S. patent #5,214,315). A unique feature of this invention is that it optimizes transition speed under reactive loading conditions typical of Si and GaAs PIN-diode arrays. We are currently upgrading the driver by modeling and specifying higher-performance power MOSFET semiconductors and reformatting the switch driver as a high-performance hybrid circuit. Integration of the discrete components comprising the switch driver onto a compact ceramic substrate will significantly improve switching speed by minimizing parasitic inductance associated with the circuit interconnects. We are employing advanced commercial software tools in order to accurately model the higher-order interconnect parasitics and semiconductor characteristics; this capability allows efficient simulation and selection of newer semiconductors best-suited to this application. It also permits accurately predicting the magnitude and effect of minute parasitic reactances, greatly reducing the time required for convergence of layout variations. Simulation studies indicate that the most recent hybrid driver design should perform at the 6 - 8 ns level for charge transfers of 15-20 nC. This figure translates to probable r.f. switching speeds in the 10 - 14 ns range for high-power silicon PIN diode arrays, or 4 - 6 ns for h.v. GaAs PIN arrays. The driver hybrid assembly is physically small and can therefore be situated in close proximity to its associated PIN arrays, minimizing detrimental transmission-line effects and electromagnetic interference. We are evaluating further candidate PIN devices and plan to requisiton the hybrid drivers once the PIN diodes have been characterized in the context of our ongoing microwave spectrometer development.