New architectures and computer-aided design algorithms for programmable logic
New architectures and computer-aided design algorithms for programmable logic
批准号:
194238-2006
负责人:
Wilton, Steven
金额:
$2.5万
依托单位国家:
加拿大
项目类别:
Discovery Grants Program - Individual
财政年份:
2007
资助国家:
加拿大
项目状态:
已结题
起止时间:
2007-01-01 至 2008-12-31
中文摘要
开发计算机芯片通常需要进入芯片加工厂。对于大多数加拿大中小型电子公司来说,进入这样一家工厂的成本是负担不起的。在拟议的研究中,我们关注另一种构建计算机芯片的方法:使用现场可编程门阵列(现场可编程门阵列)。现场可编程门阵列是一种预制的芯片,它可以在几秒钟内配置成实现几乎任何电子电路。一旦配置好,这些设备就可以包括在通信设备、计算机和消费设备等电子设备中。与制造芯片相比,使用现场可编程门阵列会导致电路变慢(大约慢3倍)。此外,只有大约1/20的电路可以安装到定制芯片上,才能安装到FPGA上。这使得现场可编程门阵列不适合许多应用。提出的研究目标是改进现场可编程门阵列的结构,使其速度更快,能够容纳更多的电路。如果成功,这将允许比以往任何时候都更多的公司使用这些设备,使它们能够以更低的成本和更快的速度创造出有竞争力的产品。除了改进现场可编程门阵列的结构外,我们还将改进设计人员用来在现场可编程门阵列上实现电路的计算机程序。这些程序中使用的算法的质量对FPGA高效实现电路的能力有很大的影响。
英文摘要
The development of computer chips normally requires access to a chip fabrication plant. The cost of accessing such a plant is out-of-reach for most small and medium-sized Canadian electronics companies. In the proposed research, we focus on an alternate way of building computer chips: using a Field-Programmable Gate Array (FPGA). An FPGA is a pre-manufactured chip which can be configured, in seconds, to implement virtually any electronic circuit. Once configured, these devices can be included in electronic devices such as communication equipment, computers, and consumer devices. Compared to fabricating a chip, using an FPGA leads to slower circuits (about 3x slower). In addition, only about 1/20 of the circuitry that can fit onto a custom chip will fit onto an FPGA. This makes FPGAs unsuitable for many applications. The goal of the proposed research is to improve the structure of FPGAs to make them faster and capable of containing more circuitry. If successful, this will allow many more companies to use these devices than ever before, allowing them to create competitive products cheaper and faster. In addition to improving the structure of FPGAs, we will also improve the computer programs that a designer uses to implement circuits on an FPGA. These quality of the algorithms used in these programs has a significant effect on the ability of the FPGA to implement circuitry efficiently.
期刊论文(0)
专著(0)
科研奖励(0)
会议论文
Bringing Field-Programmable Gate Arrays to the Masses: Towards a Design Eco-System
-
批准号:RGPIN-2017-04683
-
项目类别:Discovery Grants Program - Individual
-
资助金额:$8.45万
-
财政年份:2021
-
负责人:Wilton, Steven
-
依托单位:
Bringing Field-Programmable Gate Arrays to the Masses: Towards a Design Eco-System
-
批准号:RGPIN-2017-04683
-
项目类别:Discovery Grants Program - Individual
-
资助金额:$4.23万
-
财政年份:2020
-
负责人:Wilton, Steven
-
依托单位:
Bringing Field-Programmable Gate Arrays to the Masses: Towards a Design Eco-System
-
批准号:RGPIN-2017-04683
-
项目类别:Discovery Grants Program - Individual
-
资助金额:$4.23万
-
财政年份:2019
-
负责人:Wilton, Steven
-
依托单位:
Bringing Field-Programmable Gate Arrays to the Masses: Towards a Design Eco-System
-
批准号:RGPIN-2017-04683
-
项目类别:Discovery Grants Program - Individual
-
资助金额:$4.23万
-
财政年份:2018
-
负责人:Wilton, Steven
-
依托单位:
Bringing Field-Programmable Gate Arrays to the Masses: Towards a Design Eco-System
-
批准号:RGPIN-2017-04683
-
项目类别:Discovery Grants Program - Individual
-
资助金额:$4.23万
-
财政年份:2017
-
负责人:Wilton, Steven
-
依托单位:
New Architectures and CAD Algorithms for Field-Programmable Logic Fabrics
-
批准号:194238-2012
-
项目类别:Discovery Grants Program - Individual
-
资助金额:$3.06万
-
财政年份:2016
-
负责人:Wilton, Steven
-
依托单位:
New Architectures and CAD Algorithms for Field-Programmable Logic Fabrics
-
批准号:194238-2012
-
项目类别:Discovery Grants Program - Individual
-
资助金额:$3.06万
-
财政年份:2015
-
负责人:Wilton, Steven
-
依托单位:
Raising the Abstraction of Analysis, Debug and Optimization of High-Level Synthesis-Generated Hardware
-
批准号:447002-2013
-
项目类别:Strategic Projects - Group
-
资助金额:$7.26万
-
财政年份:2015
-
负责人:Wilton, Steven
-
依托单位:
RTL-based synthetic circuit generation for the evaluation of advanced computer-aided design algorithms and integrated circuits
-
批准号:478746-2015
-
项目类别:Collaborative Research and Development Grants
-
资助金额:$0.52万
-
财政年份:2015
-
负责人:Wilton, Steven
-
依托单位:
Raising the Abstraction of Analysis, Debug and Optimization of High-Level Synthesis-Generated Hardware
-
批准号:447002-2013
-
项目类别:Strategic Projects - Group
-
资助金额:$7.22万
-
财政年份:2014
-
负责人:Wilton, Steven
-
依托单位:
New Architectures and CAD Algorithms for Field-Programmable Logic Fabrics
-
批准号:194238-2012
-
项目类别:Discovery Grants Program - Individual
-
资助金额:$3.06万
-
财政年份:2014
-
负责人:Wilton, Steven
-
依托单位:
Raising the Abstraction of Analysis, Debug and Optimization of High-Level Synthesis-Generated Hardware
-
批准号:447002-2013
-
项目类别:Strategic Projects - Group
-
资助金额:$7.25万
-
财政年份:2013
-
负责人:Wilton, Steven
-
依托单位:
Novel algorithms for routing spare wiring structures into integrated circuits
-
批准号:448506-2013
-
项目类别:Engage Grants Program
-
资助金额:$1.2万
-
财政年份:2013
-
负责人:Wilton, Steven
-
依托单位:
New Architectures and CAD Algorithms for Field-Programmable Logic Fabrics
-
批准号:194238-2012
-
项目类别:Discovery Grants Program - Individual
-
资助金额:$3.06万
-
财政年份:2013
-
负责人:Wilton, Steven
-
依托单位:
New Architectures and CAD Algorithms for Field-Programmable Logic Fabrics
-
批准号:194238-2012
-
项目类别:Discovery Grants Program - Individual
-
资助金额:$3.06万
-
财政年份:2012
-
负责人:Wilton, Steven
-
依托单位:
New architectures and computer-aided design algorithms for programmable logic
-
批准号:194238-2006
-
项目类别:Discovery Grants Program - Individual
-
资助金额:$2.5万
-
财政年份:2011
-
负责人:Wilton, Steven
-
依托单位:
Low energy FPGA architectures and algorithms
-
批准号:428513-2011
-
项目类别:Collaborative Research and Development Grants
-
资助金额:$1.24万
-
财政年份:2011
-
负责人:Wilton, Steven
-
依托单位:
New architectures and computer-aided design algorithms for programmable logic
-
批准号:194238-2006
-
项目类别:Discovery Grants Program - Individual
-
资助金额:$2.5万
-
财政年份:2010
-
负责人:Wilton, Steven
-
依托单位:
Programmable logic based post-silicon debug infrastructure
-
批准号:381424-2009
-
项目类别:Idea to Innovation
-
资助金额:$4.37万
-
财政年份:2010
-
负责人:Wilton, Steven
-
依托单位:
Programmable logic based post-silicon debug infrastructure
-
批准号:381424-2009
-
项目类别:Idea to Innovation
-
资助金额:$9.11万
-
财政年份:2009
-
负责人:Wilton, Steven
-
依托单位:
海外基金