Low-voltage and low-power analog integrated circuits

模拟集成电路（IC）的设计者主要是由于经济原因而被迫使用占主导地位的数字互补金属氧化物半导体（CMOS）技术来开发电路。在CMOS中，电源电压继续缩小，预计（仅在几年内）在70纳米CMOS技术中低至0.7 V。即使工艺技术不需要降低电源电压，对电池供电微系统（如便携式消费电子产品、计算设备、无线通信系统和生物医学植入物）的快速依赖也导致了对在低电源电压下工作、低功耗（LV/LP）和能够高频工作的高性能ic的需求增加。在这种持续的性能改进的驱动之上，摩尔定律也在继续前进，这将推动未来的微系统在纳米CMOS工艺中实现。高性能模拟电路越来越难以在深亚微米CMOS中实现，因为固有的小信号增益和器件的余量减少，使得以前可接受的模拟拓扑和技术过时。因此，需要新的专门设计技术、新的拓扑和新的体系结构。这为本研究项目提供了动力。它探索LV和LP模拟IC的设计技术，并为未来的微系统实现开发新的高性能模拟器件。

Analog integrated circuits (IC's) designers have been forced, primarily by economics, to develop circuits using the dominant digital Complementary Metal Oxide Semiconductor (CMOS) technologies. In CMOS the supply voltage continues to scale down and it is expected (in only couple of years) to be as low as 0.7 V in 70 nm CMOS technologies. Even if the process technology didn't require reduce supply voltages, the rapidly growing reliance on battery-powered microsystems (such as portable consumer electronics, computing devices, wireless communication systems, and biomedical implants) has led to an increase need for high performance ICs that operate under low supply voltage, consume low-power (LV/LP) and capable of high frequency operation. On top of this continuous drive for performance improvement, there is also the continuing march of Moor's Law, which drives future microsystems to be implemented in nanometer CMOS process. High performance analog circuits become increasingly difficult to implement in deep sub-micron CMOS due to the reduced intrinsic small signal gain and device headroom, making previously acceptable analog topologies and technologies obsolete. Therefore, new specialized design techniques, new topologies and new architectures are needed. This provides the motivation for this research project. It explores LV and LP analog IC's design techniques and develops new high performance analog devices for future microsystems implementations.