Programmable memory systems for manycore architectures

多核芯片在计算领域占据主导地位，在台式机、服务器和移动的市场上取代了单处理器。在未来，制造商承诺提供集成数百种不同计算处理器的众核芯片。 片上存储器层次结构需要仔细设计，以确保计算单元保持忙碌。当前的存储器层次结构是用固定的数据管理策略进行硬件管理的。这种刚性与现代应用程序中复杂的访问模式不相吻合，并且及时有效地向大量核心提供数据已经变得具有挑战性。

Multicore chips dominate the computing spectrum, replacing uniprocessors throughout the desktop, server, and mobile markets. In the future, manufacturers promise to deliver manycore chips which integrate 100s of diverse compute processors. An on-chip memory hierarchy needs to be carefully designed to ensure that the compute units are kept busy. Current memory hierarchies are hardware-managed with fixed policies for data management. This rigidity doesn't dovetail with the complex access patterns in modern applications and it has become challenging to effectively supply data to the large number of cores in a timely manner.