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Transceiver Circuits for Optical Backplanes

Transceiver Circuits for Optical Backplanes
光背板收发器电路
批准号:
RGPIN-2014-04399
负责人:
Sheikholeslami, Ali
金额:
$1.82万
依托单位:
依托单位国家:
加拿大
项目类别:
Discovery Grants Program - Individual
财政年份:
2014
资助国家:
加拿大
项目状态:
已结题
起止时间:
2014-01-01 至 2015-12-31

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中文摘要
翻译
长期以来,光链路一直被认为是更轻、更清洁、更快的铜缆替代品,用于通信节点之间以公里为单位的长途数据通信。然而,在过去的十年中,随着铜缆的重量和体积的大幅增加,在较短距离的通信中,光链路已经取代了铜缆,例如数据中心的计算机之间的几米距离。今天,光链路在短至几厘米的距离上与铜链路竞争,例如在打印机电路板(PCB)上的微处理器和存储器之间,速度超过25Gb/s。在这样的速度下,铜线对电信号的衰减是如此之大,以至于无论在链路的两端包含多少电子设备,都很难在接收端恢复正确的数据。另一方面,已知光信道的衰减在这些距离上可以忽略不计,即使在更高的数据速率下也是如此。迄今为止,阻碍光学背板广泛使用的主要原因是光电接口和光电接口的成本,以及为弥补这些接口的各种缺陷而采用的周围电子设备的成本。这是除了在船上芯片的组装成本,因为更精确的校准是必要的。本提案涉及光/电接口设计(器件和电路)的创新,以及围绕这些接口的电子器件。特别地,我们建议设计光学器件,如环调制器、光电探测器和光学滤波器,以及电子电路,如反阻抗放大器(TIA)、限制放大器、均衡器、时钟和数据恢复电路。这项研究的长期目标是为光学背板展示一个完全集成的收发器。短期目标是设计、制造和测试整个收发器的单个构建模块。作为这项研究的一部分,我们还开发了一个系统级模型(在Matlab或Simulink中),其中包括所有构建块,以及它们的非理想性的主要来源。该模型将用于确定链接性能作为关键设计参数的函数。因此,我们确定了链路性能对每个设计参数的敏感性,以确定体系结构的性能极限。一旦我们确定了最终的架构,我们将朝着在电路级一次实现一个块的方向前进。在进入更高的集成级别之前,我们将单独测试每个块。
英文摘要
Optical links have long been known as lighter, cleaner, and faster alternatives to copper cables for long-haul data communication where the distance between communicating nodes is in kilometers. In the last decade, however, as the sheer weight and volume of the copper cables have increased substantially, optical links have replaced copper cables in communication over shorter distances, such as a few meters between computers in data centers. Today, optical links are competing against copper at distances as short as a few centimeters, such as those between a microprocessor and a memory on a printer circuit board (PCB), for speeds in excess of 25Gb/s. At these speeds, the copper traces attenuate the electrical signal so much that it is extremely hard to recover the correct data at the receiver end no matter how much electronics one includes at the two ends of the link. On the other hand, the attenuation of an optical channel is known to be negligible at these distances even at far higher data rates. What has prohibited so far the wider use of optical backplanes is mainly the cost of electrical to optical and optical to electrical interfaces and the surrounding electronics to compensate for various imperfections of these interfaces. This is in addition to the assembly cost of the chips on board as much more precise alignments are necessary. This proposal relates to the innovation of designs (devices and circuits) for optical/electrical interfaces, and the electronics surrounding these interfaces. In particular, we propose designs for optical devices such as the ring modulators, photo-detectors, and optical filters, and electronic circuits such as trans-impedance amplifiers (TIA), limiting amplifiers, equalizers, and clock and data recovery circuits. The long-term objective of this research is to demonstrate a fully integrated transceiver for optical backplanes. The short-term objectives are to design, fabricate, and test individual building blocks of the complete transceiver. As part of this research, we also develop a system-level model (in Matlab or Simulink) that includes all the building blocks, along with their main sources of non-idealities. This model will be used to identify the link performance as a function of key design parameters. Accordingly, we determine the sensitivity of the link performance to each design parameter in order to identify the performance limits of the architectures. Once we determine the final architecture, we will move towards implementing one block at a time in circuit level. We will test each block individually before moving on to higher levels of integration.
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Circuits and Architecture Innovations for Beyond CMOS Scaling
  • 批准号:
    RGPIN-2020-06828
  • 项目类别:
    Discovery Grants Program - Individual
  • 资助金额:
    $2.84万
  • 财政年份:
    2022
  • 负责人:
    Sheikholeslami, Ali
  • 依托单位:
Circuits and Architecture Innovations for Beyond CMOS Scaling
  • 批准号:
    RGPIN-2020-06828
  • 项目类别:
    Discovery Grants Program - Individual
  • 资助金额:
    $2.84万
  • 财政年份:
    2021
  • 负责人:
    Sheikholeslami, Ali
  • 依托单位:
Circuits for Beyond 100Gb/s Wireline Communications
  • 批准号:
    537348-2018
  • 项目类别:
    Collaborative Research and Development Grants
  • 资助金额:
    $14.66万
  • 财政年份:
    2021
  • 负责人:
    Sheikholeslami, Ali
  • 依托单位:
Circuits and Architecture Innovations for Beyond CMOS Scaling
  • 批准号:
    RGPIN-2020-06828
  • 项目类别:
    Discovery Grants Program - Individual
  • 资助金额:
    $2.84万
  • 财政年份:
    2020
  • 负责人:
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  • 依托单位:
海外基金