A study on decimal floating-point arithmetic unit through fused multiply-add architecture

自从1985年电气和电子工程师协会(IEEE)754二进制浮点标准被采用以来，每个微处理器和许多编程语言都指定了符合IEEE 754标准的浮点。最近，在金融分析、税务计算、电话计费、货币兑换、基于互联网的应用和电子商务等许多商业应用中，对十进制浮点(DFP)算术运算的需求不断增加。因此，用于DFP算术运算的规范最近被添加到IEEE浮点算术标准(IEEE754-2008)。由于许多十进制小数(例如，0.1)不能用二进制精确表示，因此以十进制格式存储数据并使用十进制算术处理数据是可取的。即使DFP算术软件消除了转换错误，DFP软件通常也比硬件中实现的等效二进制浮点(BFP)慢100到1000倍。因此，开发高效的DFP运算器硬件实现是非常重要的。 这项拟议的研究将采用用于基本运算(加法/减法、乘法和除法)的融合乘加(FMA)架构和统一的多功能块(乘法、除法、平方根、倒数和超越函数)。为了提高DFP运算器的性能，本研究将深入研究几个方面的创新，包括十进制/二进制浮点FMA的组合，基于FMA的改进的加法和乘法，以及基于FMA的高性能统一多功能块。由于FMA运算的使用非常频繁，通过FMA体系结构高效地实现DFP FMA和DFP运算器将显著提高许多商业和金融应用的性能和精度，包括银行、交易处理、风险管理、基于Internet的应用和电子商务。

Since the Institute of Electrical and Electronics Engineers (IEEE) 754 binary floating-point standard was adopted in 1985, every microprocessor and many programming languages have specified IEEE 754 compliant floating-point. Recently, there has been increased demand for decimal floating-point (DFP) arithmetic operations in many commercial applications, including financial analyses, tax calculations, phone billing, currency conversion, Internet-based applications, and e-commerce. Consequently, specifications for DFP arithmetic operations have recently been added to the IEEE Standard for Floating-Point Arithmetic (IEEE754-2008). Because many decimal fractional numbers (e.g., 0.1) cannot be exactly represented in binary, storing data in a decimal format and processing data using decimal arithmetic is desirable. Even if DFP arithmetic software eliminates conversion errors, DFP software is typically 100 to 1,000 times slower than equivalent binary floating-point (BFP) implemented in hardware. Therefore, it is very important to develop efficient hardware implementations of DFP arithmetic units. This proposed research will employ a Fused Multiply-Add (FMA) architecture for basic operations (addition/subtraction, multiplication, and division) and a unified multi-function block (multiplication, division, square-root, reciprocal, and transcendental functions). Several innovations will be thoroughly investigated in this research to improve the performance of the DFP arithmetic unit, including a combined decimal/binary floating-point FMA, improved addition and multiplication based on FMA, and a high performance unified multi-function block based on FMA. Because the FMA operation is used very frequently, efficient implementation of a DFP FMA and DFP arithmetic unit through FMA architecture will significantly improve the performance and accuracy of many commercial and financial applications, including banking, transaction processing, risk management, Internet-based applications, and e-commerce.