Automatic FPGA Interconnect Synthesis and Understanding FPGA Architecture

近年来，技术进步的快速步伐是由制造能力不断提高的数字芯片的能力所驱动的。每一代新芯片制造技术都使用更小的晶体管，并提供了计算能力的指数级提高。鲜为人知的是，设计和制造这些芯片所需的复杂性和投资也在以接近指数级的速度增长，这对未来的这一进展构成了威胁。幸运的是，被称为现场可编程门阵列（fpga）的预制、用户可编程芯片的兴起，使得使用这种奇妙的技术的风险和复杂性大大降低。事实上，绝大多数数字硬件设计工作都是使用fpga完成的；只有在非常大容量的系统（如计算机和移动设备）中才使用定制的芯片。在其他任何地方，都使用某种形式的可编程设备——要么是某种计算机处理器，要么是FPGA。我们在本研究中解决了fpga的广泛使用和采用的两个关键障碍：首先，必须将基于fpga的预制硬件的优势与其他类型的预制但可编程的数字芯片进行比较：计算机，它是用软件编程的。创建软件比创建硬件要容易得多，而且有能力编写软件的人要多得多。长期以来，研究和工业界一直在努力使硬件的创造更容易，但这些努力中的许多都是为了提高结果的质量而放弃了这种便利。然而，硬件的性能和能源效率是其相对于在处理器上运行的软件的主要优势。我们在这项研究中的目标是找到其他方法，使硬件设计过程更容易，而不会失去结果的质量。设计过程中最难做的事情之一是设计硬件计算单元之间的互连。每个这样的链接都必须根据计算的性能需求进行适当的构建。我们建议分阶段构建一个工具，帮助设计人员在面对特定性能需求时更自动地创建和改变互连。我们的最终目标是自动优化互连设计，从而使设计人员从多次重新实现的负担中解脱出来。有了这个功能，我们相信它将使设计师的工作更容易，并使高级工具能够更成功地帮助设计过程的其他部分。广泛采用fpga的第二个障碍是使预制器件有效可编程所需的灵活性成本。在大量应用中，成本可能令人望而却步：简单的可编程逻辑的成本是非可编程逻辑的10到30倍，正如我们的小组在一篇被广泛引用的论文中所报告的那样。本研究计划的第二个重点是探索一种将电路合成为fpga的全新方法，以更深入地了解实际所需的最小灵活性。我们计划通过构建一种综合方法来实现这一目标，该方法结合了许多先前分离的步骤，这些步骤用于将工程师的设计放入FPGA中。与此同时，我们将谨慎地改变可用灵活性的数量，从目前的数量减少。我们的目标是深入了解降低灵活性从而降低成本的方法。最后，我们的研究小组以FPGA的唯一开源合成工具链而闻名，在FPGA架构和CAD研究和创业中广泛使用。我们计划继续改进该软件的功能和复杂性。

The fast pace of technological advancement in recent years has been driven by the ability to fabricate digital chips with ever-increasing capability. Each new generation of chip fabrication technology uses smaller transistors and provides exponential improvements in computing capacity. It is less well known that the sophistication and investment required to design and build those chips has *also* been increasing at a near-exponential rate, threatening this progress in the future. Fortunately, the rise of pre-fabricated, user-programmable chips, known as Field-Programmable Gate Arrays (FPGAs), make it possible to use this fantastic technology with far less risk and sophistication. Indeed, the vast majority of all digital hardware design work is done using FPGAs; only in the very high volume systems (such as those in computers and mobile devices) are custom-built chips are used. Everywhere else, some form of programmable device is used - either a computer processor of some kind or an FPGA.There are two key barriers to the wider use and adoption of FPGAs that we address in this research: First, advantages of pre-fabricated FPGA-based hardware must be compared to the other kind of pre-fabricated but programmable digital chips: computers, which are programmed with software. It is much easier to create software than hardware and there many more people capable of writing software. There has long been an effort in research and industry to make the creation of hardware easier, but many of these efforts trade that ease for quality of result. However, it is that performance and energy-efficiency of hardware that are its key advantages over software running on processor. Our goal in this research is to find other ways of making the hardware design process easier, without losing the quality of the result. One of the hardest things to do in the design process is the design of interconnection between hardware computational units. Each such link must be built appropriate to the performance needs of the computation. We propose to build, in stages, a tool that helps the designer more automatically create and vary that interconnect in the face of specific performance requirements. Our ultimate goal is to automatically optimize the interconnect design, and thus release the designer from the burden of re-implementing it many times. With this capability, we believe it will make the designer's job much easier, and enable high-level tools to more successfully help with other parts of the design process.The second barrier to the wider adoption of FPGAs is the cost of the flexibility required to make a pre-fabricated device usefully programmable. The cost can be prohibitive in high volume applications: simple programmable logic is ten to thirty times the cost of non-programmable logic, as our group has reported in a widely-cited paper. The second thrust of this research proposal is to explore a fundamentally new way of synthesizing circuits into FPGAs, as a way to more deeply understand the minimum amount of flexibility actually required. We plan to do this by building a synthesis approach that combines many of the previously-separated steps that are used to take an engineer's design and put it into the FPGA. At the same time, we will carefully vary the amount of flexibility available, reducing it from its current amount. Our goal is to gain insight into ways to reduce flexibility and therefore cost.Finally, our research group is well-known for the only open-source synthesis tool chain for FPGAs, used throughout the world in FPGA architecture and CAD research and startups. We plan to continue to improve the capabilities and sophistication of this software.