Hardware/Software Codesign Flow of the 2020s

2020年的硬件/软件协同设计流程根据ITRS，我们可以预见到2020年单个芯片上有1000或更多处理器的soc。这些soc将填充未来的嵌入式系统（GPS、智能手机、视频播放器、飞机电子设备等）。设计和验证具有如此大量处理元素的硬件解决方案，以及更复杂的软件（包括数百个应用程序）将是一个巨大的挑战。可编程性、适应性、可扩展性、物理约束、可靠性和容错性是必须解决的问题，以最大限度地减少这些复杂的未来系统的周期时间和开发成本。硬件/软件（HW/SW）协同设计通过提出一个设计和验证流程来同时创建包含嵌入式系统的硬件和软件，从而研究硬件和软件组件的并发设计。近年来，特别是在未来，硬件/软件协同设计将成为工程师（硬件、软件和系统）参与复杂汽车网络系统、航空航天和航空电子系统、制造系统和嵌入式系统开发的必要条件。本提案的主要目标是通过关注五个主要问题来探索和实验本世纪20年代的硬件/软件协同设计流程：1)探索这些多处理器架构的异构性及其抽象；2)建筑探索自动化；3)在硬件/软件协同设计流程中导入遗留RTL和第三方IP块；4)改进软硬件协同验证方法；5)为航空航天和多媒体行业提供完整的软硬件协同设计和协同验证流程。

Hardware/Software Codesign Flow of the 2020sAccording to ITRS, we can foresee SoCs with 1000 or more processors on a single chip in the year 2020. These SoCs will populate the embedded systems of tomorrow (GPS, smartphones, video players, airplane electronics, etc.). Designing and verifying a hardware solution with such a huge number of processing elements, with even more complex software including hundreds of applications to exploit it, will be an enormous challenge. Programmability, adaptivity, scalability, physical constraints, reliability and fault tolerance are among the issues that must be addressed to minimize the cycle time and the development cost of these complex future systems.Hardware/Software (HW/SW) co-design investigates the concurrent design of hardware and software components, by proposing a design and verification flow for simultaneously creating hardware and software that comprises an embedded system. In recent years, and more so in the future, HW/SW co-design will be a must for engineers (hardware, software and system) involved in the development of complex automotive networked systems, aerospace and avionics systems, manufacturing systems, and embedded systems in general. The main objective of this proposal is to explore and experiment with the HW/SW co-design flow of the 2020s by focusing on five main issues:1) Exploring heterogeneity of these multi-processor architectures and their abstraction;2) Automated of the architectural exploration;3) Importing legacy RTL and third-party IP blocks within a HW/SW co-design flow;4) Improvement of the HW/SW co-verification methodology and5) A complete HW/SW co-design and co-verification flow for the aerospace and multimedia industries.