Further Development and Evaluation of an Automated Image Analysis Pipeline for Semiconductor Circuit Reverse Engineering

该提案的目标是开发一种由一套图像分析技术组成的软件工具，以帮助自动检测与集成电路(IC)中的电路相关的专利侵权行为。我们建议的软件将有助于电路提取过程的自动化，即对IC进行逆向工程，以确定其电子电路的确切结构和设计。有时需要电路提取来确定专利侵权(S)。电路提取过程是通过单独移除IC的电路层，使用扫描电子显微镜(SEM)对这些层进行成像，并分析IC版图的扫描电子显微镜图像来重建电路原理图来执行的。现有方法的主要瓶颈之一是从扫描电子显微镜图像中准确地分割出精确的IC版图，因为分割中的微小错误通常会导致重建的IC原理图中的重大错误。基于图像强度阈值的方法，例如TechInsights目前用于分割扫描电子显微镜图像的方法，在图像噪声下往往表现不佳，需要繁琐的人工检查和校正，从而导致生产成本增加。在之前的NSERC Engage项目中，我们开发了一个图像分析流水线，它包括一个图像归一化方法、两个图像过滤器和两个用于导线和垂直互连访问(VIA)的图像分割方法。初步结果表明，与TechInsights目前使用的方法相比，使用开发的管道获得的分割结果提供了更准确的IC版图分割。在这个拟议的NSERC Engage Plus项目中，我们将扩展最近开发的管道，以解决以下剩余挑战：1)不仅使用使用反向散射电子创建的扫描电子图像，而且使用使用二次电子创建的扫描电子图像；2)需要两个单独的算法来分割导线和VIA，因为图像伪影导致结果较差；3)为给定的扫描电子图像数据集选择优化的参数；以及4)水平集分割方法计算时间较长。我们将开发一种多区域分割方法

The objective of this proposal is to develop a software tool consisting of a suite of image analysis techniques tohelp automate the detection of patents infringement related to circuitry in integrated circuits (ICs). Ourproposed software will aid in automating the process of circuit extraction, where an IC is reverse engineered todetermine the exact construction and design of its electronic circuitry. Circuit extraction is sometimes requiredto determine infringement of patent(s). The process of circuit extraction is performed by individually removinglayers of circuitry of an IC, imaging the layers using a scanning electron microscope (SEM), and analysingSEM images of the IC layout to reconstruct the circuit schematics. One of the main bottlenecks in the existingapproach is the accurate segmentation of the precise IC layout from SEM images, because minute errors insegmentation usually lead to significant errors in the reconstructed IC schematics. Image intensitythreshold-based methods, such as the one used currently by TechInsights to segment the SEM images tends toperform poorly under image noise, requires tedious manual inspection and correction and consequently resultsin increased production costs. In the previous NSERC Engage project, we developed an image-analysispipeline, which consisted of an image normalization method, two image filters and two image segmentationmethods for wires and vertical interconnect accesses (VIAs). The preliminary results indicated that thesegmentation results obtained using the developed pipeline, as compared to the methods currently used byTechInsights, provided more accurate segmentations of the IC layout. In this proposed NSERC Engage Plusproject, we will expand the recently developed pipeline to address the following remaining challenges: 1)utilizing not only SEM images created using backscattered electrons, but also the ones created using secondaryelectrons; 2) requiring two separate algorithms for segmenting wires and VIAs lead to inferior results due toimage artifacts; 3) choosing optimized parameters for a given SEM image dataset; and 4) the longcomputational time of the level set segmentation method. We will develop a multi-region segmentation method