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Hardware Implementation of Cryptographic Algorithms on FPGAs and ASICs

Hardware Implementation of Cryptographic Algorithms on FPGAs and ASICs
FPGA 和 ASIC 上加密算法的硬件实现
批准号:
514921-2017
负责人:
Areibi, Shawki
金额:
$1.82万
依托单位:
依托单位国家:
加拿大
项目类别:
Engage Grants Program
财政年份:
2017
资助国家:
加拿大
项目状态:
已结题
起止时间:
2017-01-01 至 2018-12-31

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中文摘要
翻译
近年来,安全存储和传输关键数据和敏感信息的能力已被证明是业务成功的关键因素。在这个普遍的电子连接,黑客,木马,病毒和电子欺诈的时代,对安全和加密有着重要的需求。最广泛使用的对称加密算法是3DES,RC 4,Twofish和AES。非对称加密中使用的算法的例子是RSA,XTR和Diffie-Hellman。所有上述算法都可以在软件或硬件中实现。硬件加速是指使用硬件比软件更有效地执行任务。为了在当今重负载的通信网络中实现更高的性能,利用硬件加速器来实现密码算法是更有效的。这些硬件加速器倾向于从主处理器卸载加密算法的最计算密集型操作。可重构逻辑允许在硬件单元中定义新功能,结合硬件速度和效率,具有以成本有效的方式适应和科普扩展功能,改变环境要求,改进系统功能的能力,不断变化的协议和数据编码标准。该方案将进行体系结构探索,以找到有效的加密算法体系结构。在探索阶段,将生成和评估几种体系结构,以估计相互冲突的约束和目标,如面积,性能,功耗和灵活性。
英文摘要
In recent times the ability to securely store and transfer critical data and sensitive information has proved acritical factor in success of business. In this age of universal electronic connectivity, of hackers, Trojans,viruses and electronic fraud, there is an important need for security and encryption.The most widely used symmetric encryption algorithms are 3DES, RC4, Twofish and AES.Examples of algorithms used in Asymmetric encryption are RSA, XTR and Diffie-Hellman.All the above mentioned algorithms can be implemented in either software or hardware. Hardware accelerationis the use of hardware to perform a task more efficiently than is possible in software. In order to achieve higherperformance in today's heavily loaded communication networks, utilization of hardware accelerators forcryptography algorithms is more efficient. These hardware accelerators tend to offload the most computingintensive operations of encryption algorithms from the main processor.Reconfigurable logic allows the definition of new functions to be defined in hardware units, combininghardware speed and efficiency, with ability to adapt and cope in a cost effective way with expandingfunctionality, changing environmental requirements, improvements in system features, changing protocols anddata-coding standards.This proposal will perform architecture exploration to find efficient architectures for encryption algorithms.During the exploration phase, several architectures will be generated and evaluated to estimate the conflictingconstraints and objectives such as area, performance, power consumption and flexibility.
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A Smart and Efficient CAD Framework for Mapping Algorithms on Field Programmable Gate Arrays
  • 批准号:
    RGPIN-2017-04016
  • 项目类别:
    Discovery Grants Program - Individual
  • 资助金额:
    $2.04万
  • 财政年份:
    2022
  • 负责人:
    Areibi, Shawki
  • 依托单位:
A Smart and Efficient CAD Framework for Mapping Algorithms on Field Programmable Gate Arrays
  • 批准号:
    RGPIN-2017-04016
  • 项目类别:
    Discovery Grants Program - Individual
  • 资助金额:
    $2.04万
  • 财政年份:
    2021
  • 负责人:
    Areibi, Shawki
  • 依托单位:
A Smart and Efficient CAD Framework for Mapping Algorithms on Field Programmable Gate Arrays
  • 批准号:
    RGPIN-2017-04016
  • 项目类别:
    Discovery Grants Program - Individual
  • 资助金额:
    $2.04万
  • 财政年份:
    2020
  • 负责人:
    Areibi, Shawki
  • 依托单位:
A Smart and Efficient CAD Framework for Mapping Algorithms on Field Programmable Gate Arrays
  • 批准号:
    RGPIN-2017-04016
  • 项目类别:
    Discovery Grants Program - Individual
  • 资助金额:
    $2.04万
  • 财政年份:
    2019
  • 负责人:
    Areibi, Shawki
  • 依托单位:
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