The Development of Successive Approximation Register Analog-to-Digital Converter Using Time-Mode Approaches

模数转换器(ADC)几乎在我们生活的方方面面都扮演着重要的角色。ADC有多种架构可供选择。其中，闪存、增量-西格玛和逐次逼近寄存器(SAR)是占主导地位的结构。闪存模数转换器具有最高的转换速率，在有线和光纤通道上的高速数据通信等应用中广受欢迎。硅面积和功耗随着位分辨率的指数上升，以及克服比较器失配的困难，将其分辨率限制在不超过6位。Delta-Sigma模数转换器通过采样和噪声整形实现了最高分辨率。如果信号带宽很小，这些ADC是有效的。合成孔径雷达模数转换器自20世纪50年代问世以来，在推动模数转换器的最先进水平方面发挥了重要作用。虽然在20世纪之交之前，SARADC在电话和低速仪器中很流行，但它已经重新确立了自己作为最有前途的ADC架构的地位，这一架构本身就是为现代CMOS技术而设计的，其新兴应用范围从生物医学植入物到生物医学植入物，在这些植入物中，功耗对高速数据链路的转换率至关重要，并因其与技术扩展的兼容性而得到认可。合成孔径雷达模数转换器的核心功能模块是利用电容阵列实现的数模转换器。在高转换速率下，电容器阵列的动态功耗变得令人望而却步。实现电容阵列所需的硅面积也随位分辨率呈指数增长。最近，人们探索了在合成孔径雷达模数转换器中应用时间模式技术的可行性。与二进制加权电容阵列的SARADC相比，时模SARADC提供了消除电容阵列的可能性，从而大大降低了功耗和硅面积。该项目的目标是开发和原型的8位1GS/S合成孔径雷达模数转换器。

Analog-to-digital converters (ADCs) play a critical role in almost every aspect of our life. Various architecturesof ADCs are available. Among them, flash, delta-sigma, and successive approximation register (SAR) ADCsemerged as dominant architectures. Flash ADCs offer the highest conversion rate and are widely popular inapplications such as high-speed data communications over wire and optical channels. The exponentially risingsilicon area and power consumption with bit resolution and difficulties in combating comparator mismatchlimit their resolution to no more than 6 bits. Delta-sigma ADCs achieve the highest resolution by means ofoversampling and noise-shaping. These ADCs are effective if signal bandwidth is small. SAR ADCs,introduced in 1950s and sat its debut in CMOS in 1970s, has played a significant role in advancing thestate-of-the-art in ADCs since their inception. Although popular in telephony and low-speed instruments priorto the turning of 20th century, SAR ADCs have re-established themselves as the most promising ADCarchitecture inherently crafted for modern CMOS technologies with emerging applications ranging frombiomedical implants where power consumption is most critical to high-speed data links where conversion rateis pivotal, accredited to their compatibility with technology scaling. The key functional block of SAR ADCs isa digital-to-analog converter realized using capacitor arrays. At high conversion rates, the dynamic powerconsumption of the capacitor arrays becomes prohibitively large. The silicon area needed to realize capacitorarrays also rises exponentially with bit resolution. Recently the feasibility of deploying time-mode techniquesin SAR ADCs was explored. As compared with SAR ADCs with binary-weighted capacitor arrays, time-modeSAR ADCs offer the possibility of eliminating capacitor arrays so as to drastically lower power consumptionand silicon area. The objective of this project is to develop and prototype an 8-bit 1 GS/s SAR ADC using atime-mode approach.