Raising the Energy Efficiency of Mobile and Cloud Computing with FPGAs

近年来，在计算频谱的极端已经看到了急剧的增长：1）轻量级廉价的电池供电的移动的客户端（例如，膝上型计算机、平板计算机、智能电话），以及2）具有数千个服务器级机器的“云”计算场。现场可编程门阵列（FPGA）是可编程芯片，可由最终用户配置以实现数字电路。 因此，它们在计算应用程序中获得了吸引力，在这些应用程序中，它们实现了专门针对应用程序需求定制的自定义加速器。当然，FPGA的可编程性涉及开销，实际上，FPGA比功能等效的定制（即不可编程）芯片更慢，消耗更多面积，并且能效更低。 然而，虽然FPGA确实比定制芯片效率低，但从能量和计算吞吐量的角度来看，它们在实现计算方面的效率可能比处理器高出几个数量级。FPGA是一个价值60亿美元的产业，广泛应用于各种应用，特别是通信、汽车和工业电子领域。 然而，尽管FPGA在速度和能量上优于处理器，但有两个因素阻碍了FPGA在通用计算中的广泛应用：1）与定制芯片相比，它们的功耗较高，以及2）易于用途：它们的使用需要硬件设计技术和计算密集型CAD工具的知识，这使得它们成为软件工程师无法使用和/或没有吸引力的技术。 这正是本研究所要解决的两个障碍。**第一个研究重点是低功耗FPGA电路和架构。 互连是FPGA功耗的罪魁祸首。 拟议的研究以两种方式解决FPGA互连功率问题：电荷回收和一种新的信令风格：基于时间的信令。电荷回收通过将电荷存储在FPGA内未使用的导体上而不是将其倾倒到地面来节省能量。然后，当使用的导体需要进行上升过渡时，电荷被恢复。 在基于时间的信令中，特定事件的定时-转换-用于编码多个信息位。 例如，可以在16个可能的时隙之一上使用导线上的转换来发送4比特的信息。 虽然传统方法使用4条并行线来发送4位信息，但在所提出的风格中，需要在特定时间进行单次转换，从而降低能耗。所提出的信令样式需要使用数字到时间转换器（在发送器处）和时间到数字转换器（在接收器处）。 这些项目将涉及电路设计、架构和CAD技术，将驱动器/接收器物理地聚集在一起，以实现多个位到单个定时事件的有效耦合。第二个研究方向涉及FPGA可以被软件工程师用作计算平台的容易性，以提高计算吞吐量和提高能源效率。 在过去的几年里，我们一直在多伦多开发一种高级综合工具，称为LegUp，它可以将标准语言（C）的软件程序综合到FPGA硬件电路中。 该项目非常成功，全世界有700多次下载该工具。 根据该授权提出的是工具和方法：1）通过自动时钟门控和推测/预测计算执行来提高生成的硬件的质量（即速度和功耗），以及2）简化合成硬件与在英特尔和ARM处理器上运行的软件的集成，如分别在云和移动的设置中存在的那样。

Recent years have seen dramatic growth at the extreme ends of the computing spectrum: 1) lightweight inexpensive battery-powered mobile clients (e.g. laptops, tablets, smartphones), and 2) "cloud" compute farms with thousands of server-class machines. Field-programmable gate arrays (FPGAs) are programmable chips that can be configured by the end user to implement digital circuit. As such, they are gaining traction in computing applications where they implement custom accelerators that are specially tailored to an application's needs. Naturally, the programmability of FPGAs involves an overhead and indeed, FPGAs are slower, consume more area, and are less energy efficient than a functionally-equivalent custom (i.e. non-programmable) chip. However, while FPGAs are indeed less efficient than custom chips, they can be orders of magnitude more efficient than processors for implementing computations, both from the energy and computational throughput perspectives. FPGAs are a $6 billion dollar industry, and are widely used in diverse applications, especially in communications, automotive, and industrial electronics. However, despite their speed and energy supremacy over processors, two factors have impeded a broad uptake of FPGAs for general computing: 1) their high power consumption vs. custom chips, and 2) ease-of-use: their use has required knowledge of hardware design techniques and compute-intensive CAD tools, making them an inaccessible and/or unattractive technology for software engineers. These are precisely the two obstacles addressed in the proposed research.**A first research thrust centres on low-power FPGA circuits and architecture. Interconnect is the prime culprit in FPGA power consumption. The proposed research addresses FPGA interconnect power in two ways: charge recycling, and a new signalling style: time-based signalling. Charge recycling saves energy by storing charge on unused conductors within an FPGA, instead of dumping it to ground. The charge is then recovered when used conductors need to make a rising transition. In time-based signalling, the timing of a specific event -- a transition -- is used to encode multiple bits of information. For example, one can send 4 bits of information using a transition on a wire at one of 16 possible time slots. While traditional approaches use 4 parallel wires to send 4 bits of information, a single transition at a particular time is required in the proposed style, lowering energy consumption. The proposed signalling style requires the use of digital-to-time converters (at the sender) and time-to-digital converters (at the receiver). The projects will involve circuit design, architecture, and CAD techniques to cluster drivers/receivers together physically to enable the efficient coupling of multiple bits into a single timed event.**A second research direction concerns the ease with which FPGAs may be used as computing platforms targetable by software engineers to raise computational throughput and improve energy efficiency. Over the past several years, we have been developing a high-level synthesis tool at Toronto, called LegUp, which can synthesize a software program in a standard language (C) to an FPGA hardware circuit. The project has been very successful, with over 700 downloads of the tool from around the world. What is proposed under this grant are tools and methodologies to: 1) improve the quality (i.e. speed and power consumption) of the generated hardware by automated clock gating and speculative/predicated execution of computations, and 2) ease the integration of the synthesized hardware with software running on Intel and ARM processors, as are present in cloud and mobile settings, respectively.