Electronic Design Automation Algorithms for Signal Integrity Analysis of High Speed Integrated Circuits

随着技术、系统复杂性和信号速度的快速发展，人们对电子设计自动化(EDA)工具提出了很高的要求，以提供相同的效率和精度。制造工艺技术的创新显著减小了集成电路的特征尺寸，提高了芯片的封装密度。片上系统和更高的工作频率等激进的设计目标要求多学科设计方法，如电气、热和电磁分析，以准确地对高速电路的信号和电源完整性进行建模。随着频率的增加，互连的行为类似于分布式传输线，振铃、信号延迟、失真、衰减和串扰等影响会严重降低信号的完整性。这些影响可以在芯片、封装、印刷电路板和背板层面上观察到。通常，分布式互连是使用偏微分方程组来建模的，当离散化时会产生很大的方程组，这些方程组的计算代价很高。此外，由于集成电路封装密度的增加，对具有多个端口的高度耦合的互连和配电网络进行建模变得越来越重要。由于这些技术的进步，传统EDA工具的基本算法在解决现代电路设计的多学科性质和计算复杂性方面变得无效，在某些情况下已经过时。目前，多端口分布式网络的设计没有得到电路仿真器的适当处理，是信号和电源完整性分析中设计的主要瓶颈之一。**本研究方案的目的是开发先进的建模和仿真算法，以便高效、准确地分析和设计高速集成电路。这将通过扩展宏建模算法的范围来实现，以在统一的电路仿真环境中高效地对大型多端口分布式电磁系统进行建模。此外，还将开发新的并行计算和模型降阶技术，以降低大规模高速集成电路的计算复杂性。重点将是开发交互式设计验证技术，使大型复杂分布式网络的信号和电源完整性分析能够迭代和重复进行。这将带来更好的电路设计、更短的设计周期和更低的成本。

With the rapid advances of technology, system complexity and signal speeds, significant demands are placed on Electronic Design Automation (EDA) tools to provide the same efficiency and accuracy. Innovations in fabrication process technology have significantly reduced the feature sizes of integrated circuits and increased packing densities of chips. Aggressive design objectives such as system on chip coupled with increased operating frequencies require multidisciplinary design methodologies such as electrical, thermal and electromagnetic analysis to accurately model the signal and power integrity of high-speed circuits. As frequency increases, interconnects behave like distributed transmission lines and effects such as ringing, signal delay, distortion, attenuation and crosstalk can severely degrade signal integrity. These effects are observed at the chip, packaging, printed-circuit-board and backplane levels. In general, distributed interconnects are modeled using partial differential equations and when discretized produce large system of equations, which are computationally expensive to solve. Furthermore, due to the increased packing densities of integrated circuits, it is becoming essential to model highly coupled interconnect and power distribution networks with many ports. As a result of these technological advancements, the underlying algorithms of traditional EDA tools have become ineffective and in some cases obsolete in addressing the multidisciplinary nature and computational complexity of modern circuit designs. Currently, the design of multi-port distributed networks is not handled appropriately by circuit simulators and stand as one of the major bottlenecks in design in signal and power integrity analysis.** The aim of this research proposal is to develop advanced modeling and simulation algorithms for efficient and accurate analysis and design of high-speed integrated circuits. This will be achieved by extending the scope of macromodeling algorithms to efficiently model large multi-port distributed electromagnetic systems in a unified circuit simulation environment. Furthermore new parallel computing and model order reduction techniques will be developed to reduce the computational complexity of large scale high-speed integrated circuits. The emphasis will be to develop interactive design verification techniques that will enable iterative and repetitive signal and power integrity analysis of large complicated distributed networks. This will lead to better circuit designs, shorter design cycles and lower costs.